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41. 发明授权

US07196376B2 Trench-type power MOSFET with embedded region at the bottom of the gate and increased breakdown voltage 有权
标题翻译：沟槽型功率MOSFET，栅极底部嵌入区域，并提高击穿电压
公开(公告)号：US07196376B2
公开(公告)日：2007-03-27
申请号：US11097998
申请日：2005-04-04
申请人： Toru Kurosaki , Shinji Kunori , Mizue Kitada , Kosuke Ohshima , Hiroaki Shishido
发明人： Toru Kurosaki , Shinji Kunori , Mizue Kitada , Kosuke Ohshima , Hiroaki Shishido
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/66348 , H01L29/7397 , H01L29/7811
摘要： An active groove filled region 23a is kept at a portion of an active groove 22a connecting to an embedded region 24 positioned below a gate groove 83. The active groove filled region 23a connects to a source electrode film 58a so as to have the same electric potential as a source region 64. When a reverse bias is applied between a base region 32a and a conductive layer 12, a reverse bias is also applied between the embedded region 24 and the conductive layer 12; and therefore, depletion layers spread out together and a withstanding voltage is increased.
摘要翻译：活动沟槽填充区域23a保持在有源沟槽22的连接到位于栅极沟槽83下方的嵌入区域24的部分。有源沟槽填充区域23a连接到源极电极膜58a以具有与源极区域64相同的电位。当在基极区域32a和导电层12之间施加反向偏压时，在嵌入区域24和导电层12之间也施加反向偏压; 因此耗尽层一起展开并且耐受电压增加。

42. 发明授权

US08999609B2 Phase shift mask blank, method of manufacturing the same, and phase shift mask 有权
标题翻译：相移掩模空白，其制造方法和相移掩模
公开(公告)号：US08999609B2
公开(公告)日：2015-04-07
申请号：US13639686
申请日：2011-04-08
申请人： Osamu Nozawa , Hiroaki Shishido , Kazuya Sakai
发明人： Osamu Nozawa , Hiroaki Shishido , Kazuya Sakai
IPC分类号： G03F1/32 , G03F1/60 , C23C14/00 , C23C14/06 , G03F1/54 , G03F7/20 , B82Y30/00
CPC分类号： G03F1/32 , B82Y30/00 , C23C14/0036 , C23C14/0641 , G03F1/26 , G03F1/54 , G03F7/2041 , Y10S977/755
摘要： Provided are a phase shift mask blank that is improved in the irradiation durability of a light-semitransmissive film (phase shift film), made of a material containing mainly a transition metal, silicon, and nitrogen, to exposure light having a wavelength of 200 nm or less and thus can improve the mask lifetime, a method of manufacturing such a phase shift mask blank, and a phase shift mask. The phase shift mask blank is used for manufacturing a phase shift mask adapted to be applied with ArF excimer laser exposure light. The phase shift mask blank has a light-semitransmissive film on a transparent substrate. The light-semitransmissive film is an incomplete nitride film containing mainly a transition metal, silicon, and nitrogen. The content ratio of the transition metal to the transition metal and the silicon in the light-semitransmissive film is less than 9%.
摘要翻译：提供一种相位移掩模坯料，其将由主要包含过渡金属，硅和氮的材料制成的光半透射膜（相移膜）的照射耐久性提高到具有200nm波长的曝光光或更小，从而可以改善掩模寿命，制造这种相移掩模坯料的方法和相移掩模。相移掩模空白用于制造适于施加ArF准分子激光曝光光的相移掩模。相移掩模空白在透明基板上具有轻半透射膜。轻半透射膜是主要包含过渡金属，硅和氮的不完全氮化物膜。过渡金属与过渡金属和轻半透射膜中的硅的含量比小于9％。

43. 发明授权

US08431290B2 Photomask blank, photomask, and methods of manufacturing the same 有权
标题翻译：光掩模坯料，光掩模及其制造方法
公开(公告)号：US08431290B2
公开(公告)日：2013-04-30
申请号：US13126614
申请日：2009-10-27
申请人： Hiroyuki Iwashita , Atsushi Kominato , Masahiro Hashimoto , Hiroaki Shishido
发明人： Hiroyuki Iwashita , Atsushi Kominato , Masahiro Hashimoto , Hiroaki Shishido
IPC分类号： G03F1/26 , G03F1/38
CPC分类号： G03F1/50 , G03F1/46 , G03F1/54
摘要： A photomask blank is for use in manufacturing a photomask to be applied with exposure light having a wavelength of 200 nm or less. The photomask blank has a light-transmitting substrate and a light-shielding film formed thereon. The light-shielding film has a light-shielding layer containing a transition metal and silicon and a front-surface antireflection layer formed contiguously on the light-shielding layer and made of a material containing at least one of oxygen and nitrogen. The light-shielding film has a front-surface reflectance of a predetermined value or less for the exposure light and has a property capable of controlling the change width of the front-surface reflectance at the exposure wavelength to be within 2% when the thickness of the front-surface antireflection layer changes in the range of 2 nm. The material of the front-surface antireflection layer having a refractive index n and an extinction coefficient k capable of achieving such property is selected.
摘要翻译：光掩模坯料用于制造要施加具有200nm或更小的波长的曝光光的光掩模。光掩模坯料具有形成在其上的透光性基板和遮光膜。遮光膜具有含有过渡金属和硅的遮光层和在遮光层上连续形成并由含有氧和氮中的至少一种的材料制成的前表面抗反射层。遮光膜对于曝光光具有预定值以下的正面反射率，并且具有能够将曝光波长处的前表面反射率的变化宽度控制在2％以内的特性，当厚度为前表面抗反射层在2nm的范围内变化。选择具有能够实现这种特性的折射率n和消光系数k的前表面抗反射层的材料。

44. 发明申请

US20130071777A1 PHASE SHIFT MASK BLANK, METHOD OF MANUFACTURING THE SAME, AND PHASE SHIFT MASK 有权
公开(公告)号：US20130071777A1
公开(公告)日：2013-03-21
申请号：US13639686
申请日：2011-04-08
申请人： Osamu Nozawa , Hiroaki Shishido , Kazuya Sakai
发明人： Osamu Nozawa , Hiroaki Shishido , Kazuya Sakai
IPC分类号： G03F1/32 , G03F7/20
CPC分类号： G03F1/32 , B82Y30/00 , C23C14/0036 , C23C14/0641 , G03F1/26 , G03F1/54 , G03F7/2041 , Y10S977/755
摘要： Provided are a phase shift mask blank that is improved in the irradiation durability of a light-semitransmissive film (phase shift film), made of a material containing mainly a transition metal, silicon, and nitrogen, to exposure light having a wavelength of 200 nm or less and thus can improve the mask lifetime, a method of manufacturing such a phase shift mask blank, and a phase shift mask. The phase shift mask blank is used for manufacturing a phase shift mask adapted to be applied with ArF excimer laser exposure light. The phase shift mask blank has a light-semitransmissive film on a transparent substrate.The light-semitransmissive film is an incomplete nitride film containing mainly a transition metal, silicon, and nitrogen. The content ratio of the transition metal to the transition metal and the silicon in the light-semitransmissive film is less than 9%.

45. 发明申请

US20110212392A1 PHOTOMASK BLANK, PHOTOMASK, AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译： PHOTOMASK BLANK，PHOTOMASK及其制造方法
公开(公告)号：US20110212392A1
公开(公告)日：2011-09-01
申请号：US13126614
申请日：2009-10-27
申请人： Hiroyuki Iwashita , Atsushi Kominato , Masahiro Hashimoto , Hiroaki Shishido
发明人： Hiroyuki Iwashita , Atsushi Kominato , Masahiro Hashimoto , Hiroaki Shishido
IPC分类号： G03F1/00 , G03F7/20
CPC分类号： G03F1/50 , G03F1/46 , G03F1/54
摘要： A photomask blank is for use in manufacturing a photomask to be applied with exposure light having a wavelength of 200 nm or less. The photomask blank has a light-transmitting substrate and a light-shielding film formed thereon. The light-shielding film has a light-shielding layer containing a transition metal and silicon and a front-surface antireflection layer formed contiguously on the light-shielding layer and made of a material containing at least one of oxygen and nitrogen. The light-shielding film has a front-surface reflectance of a predetermined value or less for the exposure light and has a property capable of controlling the change width of the front-surface reflectance at the exposure wavelength to be within 2% when the thickness of the front-surface antireflection layer changes in the range of 2 nm. The material of the front-surface antireflection layer having a refractive index n and an extinction coefficient k capable of achieving such property is selected.
摘要翻译：光掩模坯料用于制造要施加具有200nm或更小的波长的曝光光的光掩模。光掩模坯料具有形成在其上的透光性基板和遮光膜。遮光膜具有含有过渡金属和硅的遮光层和在遮光层上连续形成并由含有氧和氮中的至少一种的材料制成的前表面抗反射层。遮光膜对于曝光光具有预定值以下的正面反射率，并且具有能够将曝光波长处的前表面反射率的变化宽度控制在2％以内的特性，当厚度为前表面抗反射层在2nm的范围内变化。选择具有能够实现这种特性的折射率n和消光系数k的前表面抗反射层的材料。

46. 发明申请

US20110081605A1 PHOTOMASK BLANK AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：照相机空白及其制造方法
公开(公告)号：US20110081605A1
公开(公告)日：2011-04-07
申请号：US12935519
申请日：2009-03-31
申请人： Hiroyuki Iwashita , Hiroaki Shishido , Atsushi Kominato , Masahiro Hashimoto
发明人： Hiroyuki Iwashita , Hiroaki Shishido , Atsushi Kominato , Masahiro Hashimoto
IPC分类号： G03F1/00
CPC分类号： G03F1/32 , G03F1/50
摘要： The present invention provides a photomask blank in which a light-shielding film consisting of a plurality of layers is provided on a light transmissive substrate, wherein a layer that is provided to be closest to the front surface is made of CrO, CrON, CrN, CrOC or CrOCN, and wherein the atom number density of the front-surface portion of the light-shielding film is 9×1022 to 14×1022 atms/cm3.
摘要翻译：本发明提供了一种光掩模坯料，其中由多层构成的遮光膜设置在透光基板上，其中设置成最靠近前表面的层由CrO，CrON，CrN， CrOC或CrOCN，其中遮光膜的前表面部分的原子数密度为9×1022〜14×1022atms / cm3。

47. 发明授权

US07282764B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07282764B2
公开(公告)日：2007-10-16
申请号：US11481247
申请日：2006-07-06
申请人： Shinji Kunori , Hiroaki Shishido , Masato Mikawa , Kosuke Ohshima , Masahiro Kuriyama , Mizue Kitada
发明人： Shinji Kunori , Hiroaki Shishido , Masato Mikawa , Kosuke Ohshima , Masahiro Kuriyama , Mizue Kitada
IPC分类号： H01L29/76
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/47 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L29/7809
摘要： A semiconductor device having high ruggedness is provided. The distance Wm2 between buried regions, positioned at the bottoms of different base diffusion regions and face each other, is set smaller than the distance Wm1 between buried regions positioned at the bottom of the same base diffusion region (Wm1>Wm2). An avalanche breakdown occurs under the bottom of the base diffusion region, and the avalanche current is not passed through a high resistance part immediately under the source diffusion region in the base diffusion region, thereby providing high withstand strength against destruction.
摘要翻译：提供了具有高耐久性的半导体器件。位于不同基底扩散区域的底部并且彼此面对的掩埋区域之间的距离Wm2 <2>被设定为小于位于该掩埋区域的掩埋区域之间的距离Wm1 < 相同的基底扩散区域（Wm1 Wm2）的底部。在基底扩散区域的底部发生雪崩击穿，并且雪崩电流不通过在基底扩散区域中的源极扩散区域的正下方的高电阻部分，从而提供高的抗破坏强度。

48. 发明申请

US20070045776A1 Semiconductor device 失效
公开(公告)号：US20070045776A1
公开(公告)日：2007-03-01
申请号：US11481247
申请日：2006-07-06
申请人： Shinji Kunori , Hiroaki Shishido , Masato Mikawa , Kosuke Ohshima , Masahiro Kuriyama , Mizue Kitada
发明人： Shinji Kunori , Hiroaki Shishido , Masato Mikawa , Kosuke Ohshima , Masahiro Kuriyama , Mizue Kitada
IPC分类号： H01L31/11
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/47 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L29/7809
摘要： A semiconductor device having high ruggedness is provided. The distance Wm2 between buried regions, positioned at the bottoms of different base diffusion regions and face each other, is set smaller than the distance Wm1 between buried regions positioned at the bottom of the same base diffusion region (Wm1>Wm2). An avalanche breakdown occurs under the bottom of the base diffusion region, and the avalanche current is not passed through a high resistance part immediately under the source diffusion region in the base diffusion region, thereby providing high withstand strength against destruction.

49. 发明申请

US20070045726A1 Semiconductor device and method for manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070045726A1
公开(公告)日：2007-03-01
申请号：US11528637
申请日：2006-09-28
申请人： Toru Kurosaki , Shinji Kunori , Mizue Kitada , Kosuke Ohshima , Hiroaki Shishido , Masato Mikawa
发明人： Toru Kurosaki , Shinji Kunori , Mizue Kitada , Kosuke Ohshima , Hiroaki Shishido , Masato Mikawa
IPC分类号： H01L29/94
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/4238 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device having high withstand voltage is provided. An active groove 22a includes a long and narrow main groove part 26 and a sub groove part 27 connected to a longitudinal side surface of the main groove part, and a buried region 24 of a second conductivity type whose height is lower than the bottom surface of the base diffusion region 32a of the second conductivity type is provided on the bottom surface of the main groove part 26. An active groove filling region 25 of the second conductivity type in contact with the base diffusion region 32a is provided in the sub groove part 27. The buried region 24 is contacted to the base diffusion region 32a through the active groove filling region 25. Since one gate groove 83 is formed by the part above the buried region 24 in one active groove 22a, the gate electrode plugs 48 are not separated, which allows the electrode pattern to be simplified.
摘要翻译：提供具有高耐压的半导体器件。活动槽22a包括长而窄的主槽部26和与主槽部的纵向侧面连接的副槽部27以及高度低于底面的第二导电型的埋入区域24 第二导电类型的基底扩散区域32a设置在主槽部分26的底表面上。在子槽部27中设置有与基底扩散区域32a相接触的第二导电类型的活动沟槽填充区域25。埋入区域24通过有源沟槽填充区域25与基极扩散区域32a接触。由于一个栅极沟槽83由一个有源槽22a中的掩埋区域24上方的部分形成，所以栅电极插塞48不分离，这允许电极图案被简化。

50. 发明申请

US20050224848A1 Semiconductor device and method for manufacturing semiconductor device 有权
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US20050224848A1
公开(公告)日：2005-10-13
申请号：US11097998
申请日：2005-04-04
申请人： Toru Kurosaki , Shinji Kunori , Mizue Kitada , Kosuke Ohshima , Hiroaki Shishido
发明人： Toru Kurosaki , Shinji Kunori , Mizue Kitada , Kosuke Ohshima , Hiroaki Shishido
IPC分类号： H01L21/331 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/739 , H01L29/78 , H01L29/872 , H01L21/8242 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/66348 , H01L29/7397 , H01L29/7811
摘要： An active groove filled region 23a is kept at a portion of an active groove 22a connecting to an embedded region 24 positioned below a gate groove 83. The active groove filled region 23a connects to a source electrode film 58a so as to have the same electric potential as a source region 64. When a reverse bias is applied between a base region 32a and a conductive layer 12, a reverse bias is also applied between the embedded region 24 and the conductive layer 12; and therefore, depletion layers spread out together and a withstanding voltage is increased.
摘要翻译：活动沟槽填充区域23a保持在有源沟槽22的连接到位于栅极沟槽83下方的嵌入区域24的部分。有源沟槽填充区域23a连接到源极电极膜58a以具有与源极区域64相同的电位。当在基极区域32a和导电层12之间施加反向偏压时，在嵌入区域24和导电层12之间也施加反向偏压; 因此耗尽层一起展开并且耐受电压增加。

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