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41. 发明申请

US20090204847A1 REPAIRABLE BLOCK REDUNDANCY SCHEME 有权
标题翻译：可修复块冗余计划
公开(公告)号：US20090204847A1
公开(公告)日：2009-08-13
申请号：US12427461
申请日：2009-04-21
申请人： Vinod Lakhani , Benjamin Louie
发明人： Vinod Lakhani , Benjamin Louie
IPC分类号： G06F11/20 , G06F12/14 , G06F12/10
CPC分类号： G11C29/808 , G11C29/76
摘要： A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection when certain input block addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address. The new addresses may contain block addresses or block and bank addresses.
摘要翻译：公开了一种用于闪速存储器件内的块替换的方案，其使用可编程查找表来存储当接收到某些输入块地址时用于块选择的新地址。每当在输入地址中检测到地址转换时，新的地址被加载到可编程熔丝锁存器中。新地址可能包含块地址或块和银行地址。

42. 发明授权

US07215571B2 Method for reducing drain disturb in programming 有权
标题翻译：减少编程中漏水干扰的方法
公开(公告)号：US07215571B2
公开(公告)日：2007-05-08
申请号：US10931689
申请日：2004-09-01
申请人： Andrei Mihnea , Vinod Lakhani
发明人： Andrei Mihnea , Vinod Lakhani
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3427 , G11C16/3418
摘要： For a multi-sectored flash memory array with bitlines spanning multiple erase blocks, a bias scheme for programming an address in any erase sector while minimizing drain voltage induced disturb to cells in unselected erase sectors sharing the same bitlines.
摘要翻译：对于具有横跨多个擦除块的位线的多扇区闪速存储器阵列，用于对任何擦除扇区中的地址进行编程的偏置方案，同时最小化漏极电压对共享相同位线的未选择擦除扇区中的单元的干扰。

43. 发明授权

US07154781B2 Contiguous block addressing scheme 有权
公开(公告)号：US07154781B2
公开(公告)日：2006-12-26
申请号：US11207017
申请日：2005-08-18
申请人： Vinod Lakhani , Benjamin Louie
发明人： Vinod Lakhani , Benjamin Louie
IPC分类号： G11C11/00
CPC分类号： G06F12/0246 , G11C16/04 , G11C29/76 , G11C29/808 , G11C29/82
摘要： An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

44. 发明授权

US07120068B2 Column/row redundancy architecture using latches programmed from a look up table 有权
公开(公告)号：US07120068B2
公开(公告)日：2006-10-10
申请号：US10206044
申请日：2002-07-29
申请人： Vinod Lakhani , Benjamin Louie
发明人： Vinod Lakhani , Benjamin Louie
IPC分类号： G11C7/00
CPC分类号： G11C29/76 , G11C29/789
摘要： A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address.

45. 发明申请

US20050281122A1 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure 有权
公开(公告)号：US20050281122A1
公开(公告)日：2005-12-22
申请号：US11212447
申请日：2005-08-26
申请人： Vinod Lakhani , Christophe Chevallier , Mathew Adsitt
发明人： Vinod Lakhani , Christophe Chevallier , Mathew Adsitt
IPC分类号： G11C7/10 , G11C8/00 , G11C8/12 , G11C16/08
CPC分类号： G11C7/1045 , G11C8/12 , G11C16/08
摘要： A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is organized into multiple main blocks each having multiple smaller blocks, emulating a disk drive. Control lines activate a number of modes. In a first mode, high-order address lines select only one block, while in a second mode, user-specified multiple blocks are selected. Blocks are selected by loading registers with selection bits or by using some of the address lines directly as selection bits. Each bit specifies one of the blocks, and each bit is independent of the others. The memory system also includes a predecoder and a controller which controls the predecoder and the registers so as to select at least two blocks of memory cells. In a third mode, all of the blocks are selected, and in a fourth mode, all blocks are deselected. Selecting multiple blocks allows simultaneous erasing, writing, and reading of multiple bytes stored in the memory.

46. 发明申请

US20050276121A1 Contiguous block addressing scheme 有权
公开(公告)号：US20050276121A1
公开(公告)日：2005-12-15
申请号：US11207017
申请日：2005-08-18
申请人： Vinod Lakhani , Benjamin Louie
发明人： Vinod Lakhani , Benjamin Louie
IPC分类号： G06F12/02 , G11C29/00 , G11C11/34
CPC分类号： G06F12/0246 , G11C16/04 , G11C29/76 , G11C29/808 , G11C29/82
摘要： An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

47. 发明申请

US20050160216A1 MEMORY SYSTEM AND METHOD FOR ASSIGNING ADDRESSES TO MEMORY DEVICES 有权
标题翻译：用于将地址分配给存储器件的存储器系统和方法
公开(公告)号：US20050160216A1
公开(公告)日：2005-07-21
申请号：US11079407
申请日：2005-03-14
申请人： Robert Norman , Vinod Lakhani
发明人： Robert Norman , Vinod Lakhani
IPC分类号： G06F12/06 , G06F12/00
CPC分类号： G06F13/1694 , G06F12/0661
摘要： A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.
摘要翻译：一种存储器系统，具有存储器控制器和通过系统总线连接到控制器的几个单独的存储器件。存储器件各自包括存储器单元阵列，用于寻址单元的寻址电路和存储每个存储器件唯一的本地地址的地址存储电路。通过选择设备中的第一个并将地址分配命令转发到所选择的设备，将本地地址依次分配给存储器设备。已经检测到地址分配命令的命令解码器将允许由控制器放置在总线上的本地地址被加载到所选择的存储器件中。该序列将继续，直到所有存储器件都被分配了本地地址，此时可以访问存储器件以执行存储器读取，编程，擦除和其他操作。

48. 发明授权

US06842380B2 Method and apparatus for erasing memory 有权
标题翻译：擦除存储器的方法和装置
公开(公告)号：US06842380B2
公开(公告)日：2005-01-11
申请号：US10228597
申请日：2002-08-27
申请人： Vinod Lakhani , Tz-Yi Liu
发明人： Vinod Lakhani , Tz-Yi Liu
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/16
摘要： The present invention provides a method and apparatus for erasing memory blocks. The apparatus includes a first plurality of memory cells formed in a substrate and a second plurality of memory cells formed in the substrate. The apparatus further includes a bias circuit adapted to provide an erasing voltage differential to the first plurality of memory cells and a compensating voltage differential to the second plurality of memory cells, wherein the erasing voltage differential is larger than the compensating voltage differential.
摘要翻译：本发明提供一种擦除存储块的方法和装置。该装置包括形成在基板中的第一多个存储单元和形成在基板中的第二多个存储单元。该装置还包括偏置电路，其适于向第一多个存储单元提供擦除电压差，以及向第二多个存储单元提供补偿电压差，其中擦除电压差大于补偿电压差。

49. 发明授权

US06567302B2 Method and apparatus for programming multi-state cells in a memory device 有权
标题翻译：用于在存储器件中编程多状态单元的方法和装置
公开(公告)号：US06567302B2
公开(公告)日：2003-05-20
申请号：US09884628
申请日：2001-06-19
申请人： Vinod Lakhani
发明人： Vinod Lakhani
IPC分类号： G11C1604
CPC分类号： G11C16/3463 , G11C11/5621 , G11C11/5628 , G11C16/10 , G11C16/3486
摘要： A method for programming multi-state floating gate transistor memory cells, also called multi-state flash cells, in a memory system is disclosed. The memory system includes control circuitry for controlling an array of multi-state flash cells which are arranged in blocks and connected together in rows and columns. The method is implemented as a series of programmable instructions stored and implemented in the memory system. According to the method groups of multi-state flash cells are incrementaly programmed. In each programming step the threshold voltage levels of the cells being programmed is raised only one state. Successive subgroups of cells are programmed to increase their threshold voltage levels in a step-by-step manner. The multi-state flash cells are programmed to store the desired data over several steps. Cells that are under-programmed in any step are reprogrammed before the method continues. Margins between the threshold voltage levels in the cells are maintained by a verification of the programmed cells. Over-programmed multi-state flash cells are identified and discarded at each programming step by calculating and retaining overshoot data.
摘要翻译：公开了一种用于在存储器系统中编程多态浮栅晶体管存储单元（也称为多状态闪存单元）的方法。存储器系统包括用于控制多个状态闪存单元的阵列的控制电路，其以块和列的形式排列并以行和列连接在一起。该方法被实现为在存储器系统中存储和实现的一系列可编程指令。根据该方法，多状态闪存单元组被增量编程。在每个编程步骤中，正被编程的单元的阈值电压电平仅升高一个状态。单元的连续子组被编程为以逐步方式增加它们的阈值电压电平。多状态闪存单元被编程为在几个步骤中存储所需的数据。在任何步骤中编程不足的单元格在方法继续之前重新编程。通过验证编程的单元来维持单元中的阈值电压电平之间的裕度。通过计算和保留过冲数据，在每个编程步骤中识别并丢弃过度编程的多状态闪存单元。

50. 发明授权

US06278642B1 Method and apparatus for limiting bitline current 有权
标题翻译：用于限制位线电流的方法和装置
公开(公告)号：US06278642B1
公开(公告)日：2001-08-21
申请号：US09435588
申请日：1999-11-08
申请人： Vinod Lakhani , Christophe J. Chevallier
发明人： Vinod Lakhani , Christophe J. Chevallier
IPC分类号： G11C700
CPC分类号： G11C29/028 , G11C7/12 , G11C16/04 , G11C16/10 , G11C29/50 , G11C2029/5006
摘要： A flash memory integrated circuit includes wordlines, bitlines, an array of floating gate transistor memory cells, and current limiters. Each floating transistor memory cell is coupled to one of the bitlines and one of the wordlines. The current limiters operate when the floating gate transistor memory cells are programmed to limit an amount of current that a defective transistor memory cell draws through the bitline coupled to the defective transistor memory cell.
摘要翻译：闪存集成电路包括字线，位线，浮栅晶体管存储单元阵列和电流限制器。每个浮动晶体管存储单元耦合到位线之一和字线之一。当浮动栅极晶体管存储单元被编程以限制缺陷晶体管存储单元通过耦合到缺陷晶体管存储单元的位线时的电流量来限制电流限制器。

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