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41. 发明授权

US07952364B2 Power noise detecting device and power noise control device using the same 失效
标题翻译：功率噪声检测装置和功率噪声控制装置使用相同
公开(公告)号：US07952364B2
公开(公告)日：2011-05-31
申请号：US12332294
申请日：2008-12-10
申请人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G01R29/26
CPC分类号： H03H1/0007 , H03K19/00346
摘要： A power noise detecting device includes a plurality of power lines, and a power noise detecting part configured to detect power noise by rectifying voltages of the plurality of power lines and converting the rectified voltages into effective voltages.
摘要翻译：电力噪声检测装置包括多个电力线，以及电力噪声检测部，被配置为通过整流多个电力线的电压并将整流电压转换为有效电压来检测电力噪声。

42. 发明授权

US07936620B2 Receiver of semiconductor memory apparatus 有权
标题翻译：半导体存储器的接收器
公开(公告)号：US07936620B2
公开(公告)日：2011-05-03
申请号：US12483413
申请日：2009-06-12
申请人： Tae-Jin Hwang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Tae-Jin Hwang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1084
摘要： A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or less than the predetermined level; a first output node voltage control unit configured to increase a voltage level of an output node when the first input transistor is turned ON; a second output node voltage control unit configured to decrease the voltage level of the output node when the second input transistor is turned ON; a third input transistor configured to increase the voltage level of the output node when an inversion signal of the input signal is equal to or less than the predetermined voltage level; and a fourth input transistor configured to decrease the voltage level of the output node when the inversion signal of the input signal is equal to or more than the predetermined voltage level.
摘要翻译：半导体存储装置的接收器包括：第一输入晶体管，其配置为当输入信号等于或大于预定电平时导通; 配置为当输入信号等于或小于预定电平时导通的第二输入晶体管; 第一输出节点电压控制单元，被配置为当所述第一输入晶体管导通时增加输出节点的电压电平; 第二输出节点电压控制单元，被配置为当所述第二输入晶体管导通时降低所述输出节点的电压电平; 第三输入晶体管，被配置为当所述输入信号的反相信号等于或小于所述预定电压电平时，增加所述输出节点的电压电平; 以及第四输入晶体管，被配置为当输入信号的反相信号等于或大于预定电压电平时降低输出节点的电压电平。

43. 发明授权

US07863957B2 Duty cycle correction circuit and semiconductor integrated circuit apparatus including the same 有权
标题翻译：占空比校正电路和包括其的半导体集成电路装置
公开(公告)号：US07863957B2
公开(公告)日：2011-01-04
申请号：US12331294
申请日：2008-12-09
申请人： Jae-Min Jang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
发明人： Jae-Min Jang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
IPC分类号： H03K5/04
CPC分类号： H03K5/1565 , H03K5/151 , H03K2005/00058
摘要： A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.
摘要翻译：占空比校正电路包括：相位分离器，被配置为控制DLL时钟信号的相位以产生上升时钟信号和下降时钟信号;时钟延迟单元，被配置为响应于时钟信号延迟上升时钟信号和下降时钟信号控制信号以产生延迟的上升时钟信号和延迟的下降时钟信号，占空比校正单元，被配置为产生校正上升时钟信号和校正下降时钟信号，该时钟信号响应于延迟的上升时钟信号的边沿定时而触发，延迟下降时钟信号，以及延迟控制单元，被配置为检测校正上升时钟信号和校正下降时钟信号的占空比，以产生控制信号。

44. 发明授权

US07795936B2 Data center tracking circuit and semiconductor integrated circuit including the same 有权
标题翻译：数据中心跟踪电路和半导体集成电路包括相同
公开(公告)号：US07795936B2
公开(公告)日：2010-09-14
申请号：US12174579
申请日：2008-07-16
申请人： Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
发明人： Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/093 , H04L7/033
摘要： A data center tracking circuit includes a clock tree, a sensing block, and a delay compensation block. The clock tree includes a plurality of clock buffers connected in series, buffers a clock, and outputs an output signal. The sensing block senses the phase change of the output signal on the basis of the clock, and outputs a sensing signal. The delay compensation block adjusts current to be supplied to the clock tree in response to the sensing signal, and adjusts the phase of the output signal.
摘要翻译：数据中心跟踪电路包括时钟树，感测块和延迟补偿块。时钟树包括串联连接的多个时钟缓冲器，缓冲时钟，并输出输出信号。感测块基于时钟感测输出信号的相位变化，并输出感测信号。延迟补偿块响应于感测信号调整提供给时钟树的电流，并调整输出信号的相位。

45. 发明授权

US07733727B2 Receiver circuit of semiconductor memory apparatus 失效
标题翻译：半导体存储器的接收电路
公开(公告)号：US07733727B2
公开(公告)日：2010-06-08
申请号：US12172108
申请日：2008-07-11
申请人： Tae-Jin Hwang , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee
发明人： Tae-Jin Hwang , Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： G11C11/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222
摘要： A receiver circuit is described herein, comprising a first data determining unit configured to detect and amplify a voltage level difference between first and second external data and generate first and second sense signals and to generate first internal data in response to the first and second sense signals, a first offset control unit configured to generate first and second offset signals in response to the first and second sense signals, the first and second offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a first code, a second data determining unit configured to detect and amplify the voltage level difference between the first and second external data to generate third and fourth sense signals and to generate second internal data in response to the third and fourth sense signals; and a second offset control unit for generating third and fourth offset signals in response to the third and fourth sense signals, the third and fourth offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a second code, wherein the first data determining unit is configured to determine setup time and hold time of the first internal data in response to the third and fourth offset signals, and wherein the second data determining unit is configured to determine setup time and hold time of the second internal data in response to the first and second offset signals.
摘要翻译：本文描述了一种接收器电路，包括：第一数据确定单元，被配置为检测和放大第一和第二外部数据之间的电压电平差，并产生第一和第二感测信号，并响应于第一和第二感测信号产生第一内部数据第一偏移控制单元，被配置为响应于第一和第二感测信号产生第一和第二偏移信号，第一和第二偏移信号在基于第一代码确定的最大电压电平和最小电压电平之间摆动，第二偏移控制单元数据确定单元，被配置为检测和放大第一和第二外部数据之间的电压电平差，以产生第三和第四感测信号，并响应于第三和第四感测信号产生第二内部数据; 以及第二偏移控制单元，用于响应于第三和第四感测信号产生第三和第四偏移信号，第三和第四偏移信号在基于第二代码确定的最大电压电平和最小电压电平之间摆动，其中第一和第二偏移信号数据确定单元被配置为响应于第三和第四偏移信号来确定第一内部数据的建立时间和保持时间，并且其中第二数据确定单元被配置为响应于确定第二内部数据的建立时间和保持时间到第一和第二偏移信号。

46. 发明授权

US08035431B2 Delay locked loop and delay locking method having burst tracking scheme 有权
标题翻译：具有脉冲串跟踪方案的延迟锁定环路和延迟锁定方法
公开(公告)号：US08035431B2
公开(公告)日：2011-10-11
申请号：US12494509
申请日：2009-06-30
申请人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/093
摘要： A Delay Locked Loop (DLL) includes a replica delay unit configured to delay an output clock to generate a feedback clock; a phase detector configured to measure a phase difference between the feedback clock and an input clock; a quantization unit configured to quantize the phase difference measured by the phase detector; and a delay unit configured to delay the input clock based on a quantization result from the quantization unit to generate the output clock.
摘要翻译：延迟锁定环（DLL）包括复制延迟单元，其被配置为延迟输出时钟以产生反馈时钟; 相位检测器，被配置为测量反馈时钟和输入时钟之间的相位差; 量化单元，被配置为量化由相位检测器测量的相位差; 以及延迟单元，被配置为基于来自量化单元的量化结果来延迟输入时钟，以产生输出时钟。

47. 发明授权

US08023356B2 Voltage level comparison circuit of semiconductor memory apparatus, voltage adjustment circuit using voltage level comparison circuit, and semiconductor memory apparatus using the same 失效
标题翻译：半导体存储装置的电压电平比较电路，使用电压电平比较电路的电压调整电路和使用其的半导体存储装置
公开(公告)号：US08023356B2
公开(公告)日：2011-09-20
申请号：US12336423
申请日：2008-12-16
申请人： Ic-Su Oh , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Ic-Su Oh , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the external voltage as the output voltage.
摘要翻译：半导体存储装置的电压调整电路包括：控制电压生成部，其被配置为响应于控制信号分配用于选择性地输出多个分配电压的外部电压作为控制电压，所述多个分配电压各自具有不同的电压电平，比较单元，被配置为包括电压供应单元，其被配置为响应于所述电平的电平而控制提供给第一节点的外部电压和第二节点，如果输出电压的电平高于参考电压的电平以及检测信号生成单元，被配置为根据输出电压和参考电压的电平来降低第一和第二节点的电位电平，并输出第二节点的电位电平作为检测信号，以及电压产生单元，被配置为根据检测信号的电位来驱动外部电压并输出外部电压作为输出电压。

48. 发明授权

US08013593B2 Voltage measuring apparatus for semiconductor integrated circuit and voltage measuring system having the same 有权
标题翻译：具有该半导体集成电路和电压测量系统的电压测量装置
公开(公告)号：US08013593B2
公开(公告)日：2011-09-06
申请号：US11961988
申请日：2007-12-20
申请人： Hyung-Soo Kim , Yong-Ju Kim , Jong-Woon Kim , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang
发明人： Hyung-Soo Kim , Yong-Ju Kim , Jong-Woon Kim , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang
IPC分类号： G01R25/00
CPC分类号： G01R31/3004 , G01R29/26
摘要： A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference clock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units.
摘要翻译：一种用于半导体集成电路的电压测量装置包括：第一延迟单元，被配置为延迟第一区域中的参考时钟;第二延迟单元，被配置为在第二区域中延迟参考时钟;以及分析单元，被配置为分析电压差基于与由第一延迟单元和第二延迟单元生成的延迟时钟信号相关联的相位，区域之间的电平。

49. 发明申请

US20100315139A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100315139A1
公开(公告)日：2010-12-16
申请号：US12494403
申请日：2009-06-30
申请人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03L7/06
CPC分类号： H03L7/0816 , G11C7/1066 , G11C7/222 , H03L7/0805
摘要： A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.
摘要翻译：半导体存储器件能够响应于读取命令和CAS延迟信息而产生输出使能信号。半导体存储器件包括：延迟锁定环，被配置为检测外部时钟信号和反馈时钟信号的相位差，产生对应于检测到的相位差的延迟控制信号，并通过延迟外部时钟信号产生DLL时钟信号延迟一段时间对应于延迟控制信号，延迟配置为响应于延迟控制信号而输出有效信号作为输出使能复位信号;以及输出使能信号发生器，其被配置为响应于输出使能复位信号复位;以及通过对外部时钟信号和DLL时钟信号进行计数，响应于读取信号和CAS等待时间信号产生输出使能信号。

50. 发明申请

US20100054047A1 SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器
公开(公告)号：US20100054047A1
公开(公告)日：2010-03-04
申请号：US12332298
申请日：2008-12-10
申请人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C7/1078 , G11C5/063 , G11C7/02 , G11C7/1084 , G11C7/1093 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028
摘要： A semiconductor memory apparatus includes a clock generator configured to generate an internal clock signal, an asynchronous data input buffer configured to buffer a data input signal through a data pad to output a buffered data signal, and a synchronous data input buffer configured to buffer the buffered data signal synchronously with the internal clock signal, wherein a length of a line, through which the internal clock signal is transmitted to the synchronous data input buffer, is configured to be substantially the same with a length of a line, through which the buffered data is transmitted to the synchronous data input buffer.
摘要翻译：一种半导体存储装置，包括被配置为产生内部时钟信号的时钟发生器，配置成通过数据焊盘缓冲数据输入信号以输出缓冲数据信号的异步数据输入缓冲器，以及被配置为缓冲缓冲的数据输入缓冲器数据信号与内部时钟信号同步，其中通过其将内部时钟信号发送到同步数据输入缓冲器的线路的长度被配置为与线路的长度基本相同，通过该线路的长度，缓冲的数据被发送到同步数据输入缓冲器。

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