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41. 发明授权

US06629047B1 Method and apparatus for flash voltage detection and lockout 失效
标题翻译：闪光电压检测和锁定的方法和装置
公开(公告)号：US06629047B1
公开(公告)日：2003-09-30
申请号：US09539475
申请日：2000-03-30
申请人： Sandeep K. Guliani , Rajesh Sundaram , Hari M. Rao , Johnny Javanifard
发明人： Sandeep K. Guliani , Rajesh Sundaram , Hari M. Rao , Johnny Javanifard
IPC分类号： G11C1300
CPC分类号： G11C5/147 , G11C16/225
摘要： A method for voltage detection and lockout. The method of one embodiment first compares a reference voltage to a supply voltage to determine whether the voltage supply voltage is greater than the reference voltage. The reference voltage is validated by determining whether the reference voltage is at least a valid voltage potential. An unlock signal is generated if the supply voltage is greater than the reference voltage and if the reference voltage is valid.
摘要翻译：一种电压检测和锁定的方法。一个实施例的方法首先将参考电压与电源电压进行比较，以确定电压电源电压是否大于参考电压。参考电压通过确定参考电压是否至少是有效的电压电位来验证。如果电源电压大于参考电压，并且参考电压有效，则产生解锁信号。

42. 发明授权

US08675442B2 Energy efficient memory with reconfigurable decoding 有权
标题翻译：具有可重构解码功能的高效能存储器
公开(公告)号：US08675442B2
公开(公告)日：2014-03-18
申请号：US13357492
申请日：2012-01-24
申请人： Hari M. Rao
发明人： Hari M. Rao
IPC分类号： G11C8/00 , G11C5/06 , G11C7/10
CPC分类号： G11C5/025 , G11C15/04
摘要： A sacrificial memory bank is added to a block of regular banks in a memory to reduce dynamic power consumption of the memory. The sacrificial bank is accessed by a set of bit lines that is substantially shorter than corresponding bit lines extending through all of the regular memory banks. Memory read and write operations, which are addressed to one of the regular banks, are deliberately redirected to the sacrificial bank having the short bit lines. Tracking circuitry identifies the regular bank that was addressed for each location in the sacrificial bank. Data is moved from the sacrificial bank to a regular bank only when a new write operation does not match the bank of the previous write operation. Dynamic power is reduced because locality of reference causes access to the sacrificial bank without having to access a regular bank for most memory read and write operations.
摘要翻译：牺牲存储体被添加到存储器中的正常存储体块中以减少存储器的动态功耗。牺牲组通过一组比特线访问，该位线显着短于延伸穿过所有常规存储体的相应位线。寻址到其中一个规则库的存储器读和写操作被故意重定向到具有短位线的牺牲库。跟踪电路识别为牺牲银行中的每个位置寻址的常规银行。只有当新的写入操作与先前写入操作的存储区不匹配时，数据才能从牺牲存储体移动到普通存储区。动态功率降低，因为参考的位置导致访问牺牲组，而无需访问常规库以进行大多数存储器读写操作。

43. 发明授权

US08665638B2 MRAM sensing with magnetically annealed reference cell 有权
标题翻译：具有磁退火参考电池的MRAM感测
公开(公告)号：US08665638B2
公开(公告)日：2014-03-04
申请号：US13179631
申请日：2011-07-11
申请人： Hari M. Rao , Xiaochun Zhu
发明人： Hari M. Rao , Xiaochun Zhu
IPC分类号： G11C11/00
CPC分类号： G11C11/1673 , G11C7/14 , G11C11/16 , G11C11/1659 , G11C13/004 , H01L43/12 , Y10T29/49117
摘要： Systems and method for reading/sensing data stored in magnetoresistive random access memory (MRAM) cells using magnetically annealed reference cells. A MRAM includes a reference circuit comprising at least one magnetic storage cell, wherein each magnetic storage cell in the MRAM is programmed to the same state. The reference circuit includes a load element coupled to the magnetic storage cell, wherein the load element is configured to establish a reference voltage during a read operation.
摘要翻译：使用磁退火参考单元读取/感测存储在磁阻随机存取存储器（MRAM）单元中的数据的系统和方法。 MRAM包括包括至少一个磁存储单元的参考电路，其中MRAM中的每个磁存储单元被编程为相同的状态。参考电路包括耦合到磁存储单元的负载元件，其中负载元件被配置为在读取操作期间建立参考电压。

44. 发明申请

US20130058172A1 Code-Based Differential Charging of Bit Lines of a Sense Amplifier 有权
标题翻译：检测放大器位线的基于码的差分充电
公开(公告)号：US20130058172A1
公开(公告)日：2013-03-07
申请号：US13224562
申请日：2011-09-02
申请人： Hari M. Rao , Esin Terzioglu , Sei Seung Yoon
发明人： Hari M. Rao , Esin Terzioglu , Sei Seung Yoon
IPC分类号： G11C7/10
CPC分类号： G11C16/28 , G11C11/41 , G11C29/026 , G11C29/028 , G11C2029/1204
摘要： A circuit includes a plurality of capacitors responsive to a plurality of latches that store a test code. A first bit line is coupled to a bit cell and coupled to a sense amplifier. A second bit line is coupled to the bit cell and coupled to the sense amplifier. A differential charge from a set of the plurality of capacitors is applied to the first bit line and to the second bit line. The set of the plurality of capacitors is determined based on the test code and the test code is independent of an output of the sense amplifier.
摘要翻译：电路包括响应于存储测试代码的多个锁存器的多个电容器。第一位线耦合到位单元并耦合到读出放大器。第二位线耦合到位单元并耦合到读出放大器。来自一组多个电容器的差分电荷被施加到第一位线和第二位线。基于测试代码确定多个电容器的集合，并且测试代码独立于读出放大器的输出。

45. 发明申请

US20110051509A1 System and Method to Manufacture Magnetic Random Access Memory 有权
标题翻译：制造磁性随机存取存储器的系统和方法
公开(公告)号：US20110051509A1
公开(公告)日：2011-03-03
申请号：US12547757
申请日：2009-08-26
申请人： Hari M. Rao , Seung Kang , Xiaochun Zhu , Sean Li , Ken Lee , Matthew M. Nowak , Robert J. Walden
发明人： Hari M. Rao , Seung Kang , Xiaochun Zhu , Sean Li , Ken Lee , Matthew M. Nowak , Robert J. Walden
IPC分类号： G11C11/14 , H01L21/00 , H01L29/82
CPC分类号： H01L27/228 , G11C11/1653 , G11C11/1659 , H01L27/0207
摘要： A system and method to manufacture magnetic random access memory is disclosed. In a particular embodiment, a method of making a magnetic tunnel junction memory system includes forming a portion of a metal layer into a source line having a substantially rectilinear portion. The method also includes coupling the source line, at the substantially rectilinear portion, to a first transistor using a first via. The first transistor is configured to supply a first current received from the source line to a first magnetic tunnel junction device. The method includes coupling the source line to a second transistor using a second via, where the second transistor is configured to supply a second current received from the source line to a second magnetic tunnel junction device.
摘要翻译：公开了制造磁随机存取存储器的系统和方法。在特定实施例中，制造磁性隧道结存储系统的方法包括将金属层的一部分形成为具有基本上直线部分的源极线。该方法还包括使用第一通孔将源极线在大致直线部分处耦合到第一晶体管。第一晶体管被配置为将从源极线接收的第一电流提供给第一磁性隧道结装置。该方法包括使用第二通孔将源极线耦合到第二晶体管，其中第二晶体管被配置为将从源极线接收的第二电流提供给第二磁性隧道结器件。

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