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41. 发明授权

US07867839B2 Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors 有权
标题翻译：降低硅锗（SiGe），高k电介质金属栅极，p型金属氧化物半导体场效应晶体管中的阈值电压（Vt）的方法
公开(公告)号：US07867839B2
公开(公告)日：2011-01-11
申请号：US12176634
申请日：2008-07-21
申请人： Xiangdong Chen , Jong Ho Lee , Weipeng Li , Dae-Gyu Park , Kenneth J. Stein , Voon-Yew Thean
发明人： Xiangdong Chen , Jong Ho Lee , Weipeng Li , Dae-Gyu Park , Kenneth J. Stein , Voon-Yew Thean
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/2652 , H01L21/823807 , H01L29/1054
摘要： Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).
摘要翻译：公开了具有最佳阈值电压（Vt）的p型硅锗（SiGe），高k电介质金属栅极，金属氧化物半导体场效应晶体管（PFET），互补金属氧化物半导体（CMOS）器件其包括PFET和形成PFET单独和CMOS器件的方法。实施例将带负电荷的离子（例如，氟（F），氯（Cl），溴（Br），碘（I）等）并入PFET的高k栅介质材料中，以便选择性地调节 PFET的负Vt（即，以减小PFET的负Vt）。

42. 发明申请

US20090291540A1 CMOS Process with Optimized PMOS and NMOS Transistor Devices 有权
标题翻译： CMOS工艺与优化的PMOS和NMOS晶体管器件
公开(公告)号：US20090291540A1
公开(公告)日：2009-11-26
申请号：US12125855
申请日：2008-05-22
申请人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
发明人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/1054 , H01L29/6659 , H01L29/66636 , H01L29/66651 , H01L29/7843 , H01L29/7848
摘要： A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
摘要翻译：半导体工艺和装置包括通过选择性地缓解PMOS器件区域（97）中的双轴拉伸应变半导体层（90）的一部分，在晶体管的沟道区域中形成具有增强的空穴迁移率的NMOS和PMOS晶体管（24,34）以形成松弛半导体层（91），然后在形成覆盖沟道区域的NMOS和PMOS栅极结构（26,36）之前外延生长双轴向应力硅锗沟道区域层（22），然后沉积接触蚀刻停止层（53-56）在NMOS和PMOS栅极结构之上。也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。

43. 发明申请

US20090256173A1 COMPLEMENTARY FIELD EFFECT TRANSISTORS HAVING EMBEDDED SILICON SOURCE AND DRAIN REGIONS 有权
标题翻译：具有嵌入式硅源和漏区的补充场效应晶体管
公开(公告)号：US20090256173A1
公开(公告)日：2009-10-15
申请号：US12103301
申请日：2008-04-15
申请人： Xiangdong Chen , Thomas W. Dyer , Haining S. Yang
发明人： Xiangdong Chen , Thomas W. Dyer , Haining S. Yang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/8258 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of a substrate. The first semiconductor region can be grown laterally adjacent to a second semiconductor region which has a lattice constant smaller than that of silicon. Layers consisting essentially of silicon can be grown epitaxially onto exposed major surfaces of the first and second semiconductor regions after which gates can be formed which overlie the epitaxially grown silicon layers. Portions of the first and second semiconductor regions adjacent to the gates can be removed to form recesses. Regions consisting essentially of silicon can be grown within the recesses to form embedded silicon regions. Source and drain regions then can be formed in the embedded silicon regions. The difference between the lattice constant of silicon and that of the underlying first and second regions results in tensile stressed silicon over the first semiconductor region and compressive stressed silicon over the second semiconductor region.
摘要翻译：提供了制造互补应力半导体器件的方法，例如具有拉伸应力通道的NFET和具有压应力通道的PFET。在这种方法中，可以在衬底的下面的半导体区域外延生长具有大于硅的晶格常数的第一半导体区域。第一半导体区域可以与具有比硅的晶格常数小的晶格常数的第二半导体区域横向生长。基本上由硅组成的层可以外延生长到第一和第二半导体区域的暴露的主表面上，之后可以形成覆盖外延生长的硅层的栅极。可以去除与栅极相邻的第一和第二半导体区域的部分以形成凹部。基本上由硅组成的区域可以在凹槽内生长以形成嵌入的硅区域。然后可以在嵌入的硅区域中形成源区和漏区。硅的晶格常数和下面的第一和第二区域的晶格常数之间的差异导致第一半导体区域上的拉伸应力硅和第二半导体区域上的压应力硅。

44. 发明申请

US20080191284A1 METHOD FOR IMPROVED FABRICATION OF A SEMICONDUCTOR USING A STRESS PROXIMITY TECHNIQUE PROCESS 失效
标题翻译：使用应力近似技术方法改进制造半导体的方法
公开(公告)号：US20080191284A1
公开(公告)日：2008-08-14
申请号：US11672572
申请日：2007-02-08
申请人： Christopher Vincent Baiocco , Xiangdong Chen , Wenzhi Gao , Young Gun Ko , Young Way Teh
发明人： Christopher Vincent Baiocco , Xiangdong Chen , Wenzhi Gao , Young Gun Ko , Young Way Teh
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/31155 , H01L21/823864 , H01L29/7843 , Y10S438/938
摘要： An improved method for applying stress proximity technique process on a semiconductor device and the improved device is disclosed. In one embodiment, the method utilizes an additional set of sidewall spacers on one or more NFET devices during the fabrication process. This protects the one or more of the NFET devices during the activation of a compressive PFET stress liner, thereby reducing the compressive forces on the one or more NFET devices, and creating a semiconductor device with improved performance.
摘要翻译：公开了一种用于在半导体器件和改进的器件上应用应力接近技术工艺的改进方法。在一个实施例中，该方法在制造过程中在一个或多个NFET器件上利用附加的一组侧壁间隔物。这在保护压电PFET应力衬垫的激活期间保护一个或多个NFET器件，由此降低一个或多个NFET器件上的压缩力，并且产生具有改进性能的半导体器件。

45. 发明申请

US20080121985A1 STRUCTURE AND METHOD TO IMPROVE SHORT CHANNEL EFFECTS IN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS 审中-公开
标题翻译：在金属氧化物半导体场效应晶体管中改善短路通道效应的结构和方法
公开(公告)号：US20080121985A1
公开(公告)日：2008-05-29
申请号：US11557145
申请日：2006-11-07
申请人： Xiangdong Chen , Dae-Gyu Park , Jae-Yoon Yoo
发明人： Xiangdong Chen , Dae-Gyu Park , Jae-Yoon Yoo
IPC分类号： H01L27/088 , H01L21/04 , H01L29/78 , H01L21/77
CPC分类号： H01L21/823814 , H01L21/823878 , H01L29/0653 , H01L29/1083 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7833
摘要： Disclosed are embodiments of improved MOSFET and CMOS structures that provides for increased control over short channel effects. Also disclosed are embodiments of associated methods of forming these structures. The embodiments suppress short channel effects by incorporating buried isolation regions into a transistor below source/drain extension regions and between deep source/drain regions and the channel region and, particularly, between deep source/drain regions and the halo regions. Buried isolation regions between the deep source/drain regions and the channel region minimize drain induced barrier lowering (DIBL) as well as punch through. Additionally, because the deep source/drain regions and halo regions are separated by the buried isolation regions, side-wall junction capacitance and junction leakage are also minimized.
摘要翻译：公开了改进的MOSFET和CMOS结构的实施例，其提供对短沟道效应的增加的控制。还公开了形成这些结构的相关方法的实施例。这些实施例通过将掩埋隔离区域并入到源极/漏极延伸区域之下以及深源极/漏极区域和沟道区域之间，特别是在深源极/漏极区域和晕圈区域之间的晶体管中来抑制短沟道效应。在深源极/漏极区域和沟道区域之间的埋置隔离区域最小化漏极引起的屏障降低（DIBL）以及穿通。此外，由于深源极/漏极区域和晕圈区域被掩埋隔离区域分开，所以侧壁结电容和结漏电也被最小化。

46. 发明授权

US07361539B2 Dual stress liner 有权
标题翻译：双重应力衬垫
公开(公告)号：US07361539B2
公开(公告)日：2008-04-22
申请号：US11383560
申请日：2006-05-16
申请人： Xiangdong Chen , Haining S. Yang
发明人： Xiangdong Chen , Haining S. Yang
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823807 , H01L29/7842
摘要： A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second source region, a second drain region and a second gate conductor overlying the second channel region. The first and second gate conductors are portions of a single elongated conductive member extending over both the first and second channel regions. A first stressed film overlies the first FET, the first stressed film applying a stress having a first value to the first channel region. A second stressed film overlies the second FET, the second stressed film applying a stress having a second value to the second channel region. The second value is substantially different from the first value. In addition, the first and second stressed films abut each other at a common boundary and present a substantially co-planar major surface at the common boundary.
摘要翻译：提供一种半导体器件结构，其包括第一场效应晶体管（“FET”），其具有第一沟道区，第一源极区，第一漏极区和覆盖第一沟道区的第一栅极导体。包括第二FET，其具有覆盖第二沟道区的第二沟道区，第二源极区，第二漏极区和第二栅极导体。第一和第二栅极导体是在第一和第二沟道区两者上延伸的单个细长导电构件的部分。第一应力膜覆盖第一FET，第一应力膜将具有第一值的应力施加到第一沟道区。第二应力膜覆盖第二FET，第二应力膜向第二沟道区施加具有第二值的应力。第二个值与第一个值大不相同。此外，第一和第二应力膜在共同边界处彼此邻接并且在共同边界处呈现基本上共平面的主表面。

47. 发明申请

US20080001182A1 IMPROVED CMOS DEVICES WITH STRESSED CHANNEL REGIONS, AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：改进的具有应力通道区域的CMOS器件及其制造方法
公开(公告)号：US20080001182A1
公开(公告)日：2008-01-03
申请号：US11427495
申请日：2006-06-29
申请人： Xiangdong Chen , Thomas W. Dyer , Kenneth Settlemyer , Haining S. Yang
发明人： Xiangdong Chen , Thomas W. Dyer , Kenneth Settlemyer , Haining S. Yang
IPC分类号： H01L29/76 , H01L27/148
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/30604 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/045 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/78684 , H01L29/78696
摘要： The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.
摘要翻译：本发明涉及具有应力通道区域的改进的互补金属氧化物半导体（CMOS）器件。具体地，每个改进的CMOS器件包括具有位于半导体器件结构中的沟道区的场效应晶体管（FET），其具有沿着第一组等效晶面中的一个取向的顶表面和沿着第二，不同组的等效晶面。这种附加表面可以通过晶体蚀刻容易地形成。此外，具有固有压缩或拉伸应力的一个或多个应力层位于半导体器件结构的附加表面上，并且被布置和构造成将拉应力或压应力施加到FET的沟道区。这样的应力层可以通过具有与半导体器件结构不同的晶格常数的半导体材料的假晶生长来形成。

48. 发明申请

US20070254420A1 SOURCE/DRAIN IMPLANTATION AND CHANNEL STRAIN TRANSFER USING DIFFERENT SIZED SPACERS AND RELATED SEMICONDUCTOR DEVICE 审中-公开
标题翻译：使用不同尺寸的间距和相关半导体器件的源/漏极植入和通道应变传输
公开(公告)号：US20070254420A1
公开(公告)日：2007-11-01
申请号：US11380743
申请日：2006-04-28
申请人： Atul Ajmera , Christopher Baiocco , Xiangdong Chen , Thomas Dyer , Sunfei Fang , Wenzhi Gao
发明人： Atul Ajmera , Christopher Baiocco , Xiangdong Chen , Thomas Dyer , Sunfei Fang , Wenzhi Gao
IPC分类号： H01L21/338 , H01L21/20 , H01L29/76
CPC分类号： H01L21/823425 , H01L21/823412 , H01L21/823468 , H01L21/823807 , H01L21/823864 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： Methods for source/drain implantation and strain transfer to a channel of a semiconductor device and a related semiconductor device are disclosed. In one embodiment, the method includes using a first size spacer for deep source/drain implantation adjacent a gate region of a semiconductor device; and using a second, smaller size spacer for silicide formation adjacent the gate region and transferring strain from a stress liner to a channel underlying the gate region. One embodiment of a semiconductor device may include a gate region atop a substrate; a spacer including a spacer core and an outer spacer member about the spacer core; a deep source/drain region within the substrate and distanced from the spacer; and a silicide region within the substrate and overlapping and extending beyond the deep source/drain region, the silicide region aligned to the spacer.
摘要翻译：公开了用于源极/漏极注入和应变转移到半导体器件和相关半导体器件的沟道的方法。在一个实施例中，该方法包括使用与半导体器件的栅极区域相邻的深源极/漏极注入的第一尺寸间隔物; 并且使用第二较小尺寸的间隔物，用于邻近栅极区域的硅化物形成，并将应变从应力衬垫转移到栅极区域下方的沟道。半导体器件的一个实施例可以包括位于衬底顶部的栅极区域; 间隔件，其包括间隔件芯和围绕所述间隔件芯的外部间隔件; 衬底内的深源极/漏极区域，并远离间隔物; 以及衬底内的硅化物区域，并且重叠并延伸超过深源极/漏极区域，硅化物区域与间隔物对准。

49. 发明申请

US20070051996A1 METHOD OF FORMING A MOSFET WITH DUAL WORK FUNCTION MATERIALS 有权
标题翻译：形成具有双功能功能材料的MOSFET的方法
公开(公告)号：US20070051996A1
公开(公告)日：2007-03-08
申请号：US11553072
申请日：2006-10-26
申请人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing Ouyang
发明人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing Ouyang
IPC分类号： H01L29/94
CPC分类号： H01L29/66181 , H01L27/10864
摘要： A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.
摘要翻译：在DRAM单元中使用的用于保持低总漏电流并提供足够的驱动电流的垂直传输晶体管与制造这种器件的方法一起被描述。晶体管栅极被设计代替通道。用于DRAM单元的垂直传输晶体管包括具有不同功函数的两个栅极材料。存储节点附近的栅极材料为n型掺杂多晶硅。位线扩散附近的栅极材料由具有比n-多晶硅更高的功函数的硅化物或金属制成。该新颖的器件结构显示出几个优点：沟道掺杂减少，同时保持高Vt和低的亚阈值漏电流; 载流子迁移率随着沟道掺杂的降低而提高; 减少了器件的体效，提高了回写电流; 并且由于低通道掺杂，子阈值摆幅减小。

50. 发明申请

US20070045611A1 MOSFET WITH LATERALLY GRADED CHANNEL REGION AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：具有横向分级通道区域的MOSFET及其制造方法
公开(公告)号：US20070045611A1
公开(公告)日：2007-03-01
申请号：US11162126
申请日：2005-08-30
申请人： Huilong Zhu , Xiangdong Chen
发明人： Huilong Zhu , Xiangdong Chen
IPC分类号： H01L29/06
CPC分类号： H01L21/26506 , H01L21/28132 , H01L29/1054 , H01L29/6656 , H01L29/66636 , H01L29/66659 , H01L29/66742 , H01L29/7834 , H01L29/78684 , H01L29/78696
摘要： The present invention relates generally to a semiconductor device having a channel region comprising a semiconductor alloy of a first semiconductor material and a second, different material, and wherein atomic distribution of the second material in the channel region is graded along a direction that is substantially parallel to a substrate surface in which the semiconductor device is located. Specifically, the semiconductor device comprises a field effect transistor (FET) that has a SiGe channel with a laterally graded germanium content.
摘要翻译：本发明一般涉及具有包括第一半导体材料和第二不同材料的半导体合金的沟道区的半导体器件，并且其中沟道区中的第二材料的原子分布沿着基本平行的方向分级到半导体器件所在的衬底表面。具体地，半导体器件包括具有横向渐变的锗含量的SiGe沟道的场效应晶体管（FET）。

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