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41. 发明授权

US07318181B2 ROM-based controller monitor in a memory device 有权
标题翻译：基于ROM的控制器监视器在存储器件中
公开(公告)号：US07318181B2
公开(公告)日：2008-01-08
申请号：US11166500
申请日：2005-06-24
申请人： Giovanni Naso , Pasquale Pistilli , Luca De Santis , Pasquale Conenna
发明人： Giovanni Naso , Pasquale Pistilli , Luca De Santis , Pasquale Conenna
IPC分类号： G11C29/00
CPC分类号： G11C29/12015 , G11C16/04 , G11C29/16 , G11C29/48 , G11C29/50004
摘要： A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be monitored according to different test modes. The ROM-based microcontroller is triggered by a clock that can be connected to an internal fixed frequency oscillator or to an external clock source for which the frequency can be varied from 0 Hz to any frequency required by the application. The circuit outputs state machine status data, read only memory addresses, and memory status information in a series of multiplexing operations to provide a tester with the ability to determine the state of a memory device during various memory operations.
摘要翻译：用于在由基于ROM的微控制器管理的编程/擦除操作期间监视存储器件的活动的电路。可以根据不同的测试模式监控不同的信号。基于ROM的微控制器由可连接到内部固定频率振荡器或外部时钟源的时钟触发，频率可以从0 Hz变化到应用所需的任何频率。电路在一系列复用操作中输出状态机状态数据，只读存储器地址和存储器状态信息，以向测试者提供在各种存储器操作期间确定存储器件的状态的能力。

42. 发明申请

US20060083061A1 Flash cell fuse circuit 有权
公开(公告)号：US20060083061A1
公开(公告)日：2006-04-20
申请号：US11293760
申请日：2005-12-02
申请人： Goiovanni Santin , Giovanni Naso
发明人： Goiovanni Santin , Giovanni Naso
IPC分类号： G11C14/00
CPC分类号： G11C29/789 , G11C16/0441 , G11C16/20 , G11C16/26 , G11C17/18
摘要： Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory applications. The fuse circuits include a floating-gate memory cell for storing a data value and a fuse latch to hold and transfer the data value of the floating-gate memory cell at power-up or upon request. A latch driver circuit can write data values to the fuse latch without affecting the data value stored in the floating-gate memory cell. The fuse circuits can further utilize the same structure, pitch, bit-line organization and word-line organization as the memory device's memory array. As the fuse circuits can utilize the same structure and organization, the data value of the fuse circuit can be programmed, erased and read using the same data path as the regular memory array.

43. 发明授权

US06977852B2 ROM-based controller monitor in a memory device 有权
标题翻译：基于ROM的控制器监视器在存储器件中
公开(公告)号：US06977852B2
公开(公告)日：2005-12-20
申请号：US10696973
申请日：2003-10-30
申请人： Giovanni Naso , Pasquale Pistilli , Luca De Santis , Pasquale Conenna
发明人： Giovanni Naso , Pasquale Pistilli , Luca De Santis , Pasquale Conenna
IPC分类号： G01R31/28 , G06F9/00 , G06F9/24 , G06F11/00 , G06F15/177 , G11C7/00 , G11C17/00 , G11C29/16 , G11C29/48
CPC分类号： G11C29/12015 , G11C16/04 , G11C29/16 , G11C29/48 , G11C29/50004
摘要： A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be monitored according to different test modes. The ROM-based microcontroller is triggered by a clock that can be connected to an internal fixed frequency oscillator or to an external clock source for which the frequency can be varied from 0 Hz to any frequency required by the application. The circuit outputs state machine status data, read only memory addresses, and memory status information in a series of multiplexing operations to provide a tester with the ability to determine the state of a memory device during various memory operations.
摘要翻译：用于在由基于ROM的微控制器管理的编程/擦除操作期间监视存储器件的活动的电路。可以根据不同的测试模式监控不同的信号。基于ROM的微控制器由可连接到内部固定频率振荡器或外部时钟源的时钟触发，频率可以从0 Hz变化到应用所需的任何频率。电路在一系列复用操作中输出状态机状态数据，只读存储器地址和存储器状态信息，以向测试者提供在各种存储器操作期间确定存储器件的状态的能力。

44. 发明授权

US06717862B2 Flash memory sector tagging for consecutive sector erase or bank erase 有权
标题翻译：闪存扇区标记用于连续扇区擦除或存储体擦除
公开(公告)号：US06717862B2
公开(公告)日：2004-04-06
申请号：US10229921
申请日：2002-08-28
申请人： Giovanni Naso , Giovanni Santin , Pasquale Pistilli
发明人： Giovanni Naso , Giovanni Santin , Pasquale Pistilli
IPC分类号： G11C1604
CPC分类号： G11C29/12005 , G11C16/04 , G11C16/16 , G11C29/12
摘要： Methods and apparatus to facilitate erasure of multiple sectors of a memory device without the need for externally-supplied erase potentials are advantageous for device testing. During a scan of sector addresses, sector tagging blocks of a memory device provide an output signal to a write state machine indicating whether the addressed sector is tagged for erasure. The sector tagging blocks facilitate resetting of tags on a global basis and setting of tags on a single, bank-wide and/or global basis. Once initiated, the erase operation proceeds to erase each tagged sector of the memory device in sequence without the need for externally-supplied erase potentials and without the need for further direction of the tester hardware. The methods are particularly useful for erasing all sectors of a memory device or all sectors of one memory bank of the memory device.
摘要翻译：便于擦除存储器件的多个扇区而不需要外部提供的擦除电位的方法和装置对于器件测试是有利的。在扇区地址的扫描期间，存储器件的扇区标记块向写入状态机提供指示被寻址扇区是否被标记为擦除的输出信号。扇区标记块有助于在全球范围内重置标签，并在单个银行范围和/或全局基础上设置标签。一旦启动，擦除操作继续进行以顺序地擦除存储器件的每个标记扇区，而不需要外部提供的擦除电位，并且不需要测试仪硬件的进一步的方向。这些方法对于擦除存储器件的所有扇区或存储器件的一个存储器组的所有扇区特别有用。

45. 发明授权

US06654272B2 Flash cell fuse circuit 有权
公开(公告)号：US06654272B2
公开(公告)日：2003-11-25
申请号：US09943643
申请日：2001-08-30
申请人： Giovanni Santin , Giovanni Naso
发明人： Giovanni Santin , Giovanni Naso
IPC分类号： G11C1700
CPC分类号： G11C17/18 , G11C16/20 , G11C16/26
摘要： Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory applications. The fuse circuits include a floating-gate memory cell for storing a data value and a fuse latch to hold and transfer the data value of the floating-gate memory cell at power-up or upon request. A latch driver circuit can write data values to the fuse latch without affecting the data value stored in the floating-gate memory cell. The fuse circuits can further utilize the same structure, pitch, bit-line organization and word-line organization as the memory device's memory array. As the fuse circuits can utilize the same structure and organization, the data value of the fuse circuit can be programmed, erased and read using the same data path as the regular memory array.

46. 发明授权

US5056063A Active sense amplifier with dynamic pre-charge transistor 失效
标题翻译：具有动态预充电晶体管的有源读出放大器
公开(公告)号：US5056063A
公开(公告)日：1991-10-08
申请号：US529292
申请日：1990-05-29
申请人： Giovanni Santin , Giovanni Naso
发明人： Giovanni Santin , Giovanni Naso
IPC分类号： G11C7/06 , G11C16/26
CPC分类号： G11C7/067 , G11C16/26
摘要： A sense amplifier including a pair of P-conductivity-type current-mirror transistors, a N-conductivity-type reference transistor and a cascode-connected N-conductivity-type transistor and inverter connected according to prior-art. The amplifier also includes a N-conductivity-type pre-charge transistor with source-drain path connected in parallel with the source-drain path of P-conductivity-type mirror load transistor. The gate of the pre-charge transistor is connected to the gate of the N-conductivity-type cascode transistor, which is also connected to the output of cascode inverter.The pre-charge transistor functions to bypass the mirror load transistor when a discharged bitline is selected. As a result, the current charging the bitline capacitance is increased and the time needed for charging is decreased. As an additional benefit, the bitline-charging current through the pre-charge transistor bypasses the current mirror load transistor, greatly diminishing the probability of a read error being mirrored to the output of sense amplifier.
摘要翻译：一种读出放大器，包括一对P导电型电流镜晶体管，N导电型参考晶体管和根据现有技术连接的共源共栅型N导电型晶体管和反相器。该放大器还包括一个N导电型预充电晶体管，源极 - 漏极路径与P型导电型镜面负载晶体管的源极 - 漏极路径并联连接。预充电晶体管的栅极连接到N导电型共源共栅晶体管的栅极，其也连接到共源共栅反相器的输出。当选择放电位线时，预充电晶体管用于旁路镜像负载晶体管。结果，对位线电容的电流充电被增加，并且充电所需的时间减少。作为额外的好处，通过预充电晶体管的位线充电电流绕过电流镜像负载晶体管，大大降低了读出误差被镜像到读出放大器的输出的概率。

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