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41. 发明授权

US07627698B2 Methods and apparatus for providing data transfer control 有权
公开(公告)号：US07627698B2
公开(公告)日：2009-12-01
申请号：US11830448
申请日：2007-07-30
申请人： Edwin Franklin Barry , Edward A. Wolff
发明人： Edwin Franklin Barry , Edward A. Wolff
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/126 , G06F13/28
摘要： A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special “event-action” registers. Transfer controllers are also described which can cooperate to perform “DMA-to-DMA” transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other.

42. 发明授权

US4354225A Intelligent main store for data processing systems 失效
标题翻译：数据处理系统的智能主要存储
公开(公告)号：US4354225A
公开(公告)日：1982-10-12
申请号：US83648
申请日：1979-10-11
申请人： Gideon Frieder , David T. Hughes , Mark H. Kline , John T. Liebel, Jr. , David P. Meier , Edward A. Wolff
发明人： Gideon Frieder , David T. Hughes , Mark H. Kline , John T. Liebel, Jr. , David P. Meier , Edward A. Wolff
IPC分类号： G06F11/273 , G06F13/28 , G06F15/80 , G06F13/00 , G06F15/16
CPC分类号： G06F13/28 , G06F11/2736 , G06F15/8007
摘要： A data processing system comprising an active and intelligent main store including a main memory, a main store controller for accessing the main memory in a manner allowing different address and data structures, and a main store bus connected to the controller. At least one processor of a first type is connected to the main store bus, this being an auxiliary processor for performing input-output and other operations. At least one processor of a second type also is connected to the main store bus, this being an execution processor for fetching, decoding and executing instructions. All or some of either or both of the auxiliary processors and execution processors may be different. A supervisory processor for initiating configuring and monitoring the system is connected to the main store bus. A communication bus is connected to the processors of the first and second types and to the supervisory processor. A diagnostic bus connects the supervisory processor to each of the processors of the first and second types. An input-output bus ensemble is connected to the supervisory processor and to each auxiliary processor. At least one device and associated device controller can be connected to the input-output bus ensemble. At least one direct memory access controller can be connected between the main store bus and the input-output bus ensemble.
摘要翻译：一种数据处理系统，包括主动和智能主存储，其包括主存储器，以存储不同地址和数据结构的方式访问主存储器的主存储控制器以及连接到控制器的主存储总线。第一类型的至少一个处理器连接到主存储总线，这是用于执行输入输出和其他操作的辅助处理器。至少一个第二类型的处理器也连接到主存储总线，这是用于获取，解码和执行指令的执行处理器。辅助处理器和执行处理器中的一个或两个的全部或一部分可以不同。用于启动配置和监视系统的监控处理器连接到主存储总线。通信总线连接到第一类型和第二类型的处理器以及监控处理器。诊断总线将监控处理器连接到第一和第二类型的每个处理器。输入 - 输出总线系统连接到监控处理器和每个辅助处理器。至少一个设备和相关设备控制器可以连接到输入 - 输出总线系统。至少一个直接存储器访问控制器可以连接在主存储总线和输入 - 输出总线组合之间。

43. 发明授权

US07302504B2 Methods and apparatus for providing data transfer control 有权
标题翻译：提供数据传输控制的方法和装置
公开(公告)号：US07302504B2
公开(公告)日：2007-11-27
申请号：US11533897
申请日：2006-09-21
申请人： Edwin Franklin Barry , Edward A. Wolff
发明人： Edwin Franklin Barry , Edward A. Wolff
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/126 , G06F13/28
摘要： A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special “event-action” registers. Transfer controllers are also described which can cooperate to perform “DMA-to-DMA” transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other.
摘要翻译：描述了用于在数据处理系统内改进数据传输控制的各种有利机制。描述了一种DMA控制器，其被实现为支持多个传输控制器的多处理传输引擎，其可以独立地或协作地执行数据传输，每个传输控制器充当自主处理器，将DMA指令提取并分派给多个执行单元。特别地，提供了用于启动和控制数据传输序列的机制，以及自动获取被顺序解码但并行执行的DMA指令的过程。每个传输控制器内的双传送执行单元与独立的传输计数器一起被用于允许源和目标地址生成的解耦，并允许一个传送执行单元中的多个传输指令与另一个传输中的单个传输指令并行操作单元。通过使用特殊信号量操作，信号和消息同步，可以使用SIGNAL和WAIT类型指令明确地调用，或者通过使用特殊的“事件动作”寄存器来隐式地调用源和目标之间的数据流改进。还描述了可以协作执行“DMA到DMA”传输的传输控制器。传输控制器可以使用消息级同步来相互同步。

44. 发明授权

US07130934B2 Methods and apparatus for providing data transfer control 有权
公开(公告)号：US07130934B2
公开(公告)日：2006-10-31
申请号：US11100697
申请日：2005-04-07
申请人： Edwin Franklin Barry , Edward A. Wolff
发明人： Edwin Franklin Barry , Edward A. Wolff
IPC分类号： G06F13/00
CPC分类号： G06F13/126 , G06F13/28
摘要： A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special “event-action” registers. Transfer controllers are also described which can cooperate to perform “DMA-to-DMA” transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other.

45. 发明授权

US06912608B2 Methods and apparatus for pipelined bus 有权
标题翻译：流水线总线的方法和装置
公开(公告)号：US06912608B2
公开(公告)日：2005-06-28
申请号：US10131941
申请日：2002-04-25
申请人： Edward A. Wolff , David Baker , Bryan Garnett Cope , Edwin Franklin Barry
发明人： Edward A. Wolff , David Baker , Bryan Garnett Cope , Edwin Franklin Barry
IPC分类号： G06F15/80 , G06F13/00
CPC分类号： G06F15/8007
摘要： Techniques for a pipelined bus which provides a very high performance interface to computing elements, such as processing elements, host interfaces, memory controllers, and other application-specific coprocessors and external interface units. The pipelined bus is a robust interconnected bus employing a scalable, pipelined, multi-client topology, with a fully synchronous, packet-switched, split-transaction data transfer model. Multiple non-interfering transfers may occur concurrently since there is no single point of contention on the bus. An aggressive packet transfer model with local conflict resolution in each client and packet-level retries allows recovery from collisions and buffer backups. Clients are assigned unique IDs, based upon a mapping from the system address space allowing identification needed for quick routing of packets among clients.
摘要翻译：用于流水线总线的技术，其为诸如处理元件，主机接口，存储器控制器和其他特定于应用的协处理器和外部接口单元的计算元件提供非常高的性能接口。流水线总线是一种强大的互连总线，采用可扩展的，流水线式的多客户端拓扑，具有完全同步的分组交换，分组交易数据传输模型。多个非干扰传输可能同时发生，因为总线上没有单一的争用点。在每个客户端和数据包级重试中，具有本地冲突解决能力的攻击性数据包传输模型允许从冲突和缓冲备份恢复。基于从系统地址空间的映射，客户端被分配唯一的ID，允许在客户端之间快速路由分组所需的标识。

46. 发明授权

US4527237A Data processing system 失效
公开(公告)号：US4527237A
公开(公告)日：1985-07-02
申请号：US483444
申请日：1983-04-14
申请人： Gideon Frieder , David T. Hughes , Mark H. Kline , John T. Liebel, Jr. , David P. Meier , Edward A. Wolff
发明人： Gideon Frieder , David T. Hughes , Mark H. Kline , John T. Liebel, Jr. , David P. Meier , Edward A. Wolff
IPC分类号： G06F11/273 , G06F13/28 , G06F15/16 , G06F15/80 , G06F13/00
CPC分类号： G06F13/28 , G06F11/2736 , G06F15/161 , G06F15/8007
摘要： A data processing system comprising an active and intelligent main store including a main memory, a main store controller for accessing the main memory in a manner allowing different address and data structures, and a main store bus connected to the controller. At least one processor of a first type is connected to the main store bus, this being an auxiliary processor for performing input-output and other operations. At least one processor of a second type also is connected to the main store bus, this being an execution processor for fetching, decoding and executing instructions. All or some of either or both of the auxiliary processors and execution processors may be different. A supervisory processor for initiating configuring and monitoring the system is connected to the main store bus. A communication bus is connected to the processors of the first and second types and to the supervisory processor. A diagnostic bus connects the supervisory processor to each of the processors of the first and second types. An input-output bus ensemble is connected to the supervisory processor and to each auxiliary processor. At least one device and associated device controller can be connected to the input-output bus ensemble. At least one direct memory access controller can be connected between the main store bus and the input-output bus ensemble.

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