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41. 发明授权

US07402859B2 Field effect semiconductor switch and method for fabricating it 有权
标题翻译：场效应半导体开关及其制造方法
公开(公告)号：US07402859B2
公开(公告)日：2008-07-22
申请号：US11079884
申请日：2005-03-15
申请人： Joerg Vollrath , Marcin Gnat , Ralf Schneider , Stephan Schroeder
发明人： Joerg Vollrath , Marcin Gnat , Ralf Schneider , Stephan Schroeder
IPC分类号： H01L27/108 , H01L21/336
CPC分类号： H01L29/78696 , H01L27/10867 , H01L27/10873 , H01L29/0649 , H01L29/1037 , H01L29/42384 , H01L29/66757 , H01L29/66772 , H01L29/78606 , H01L29/78618
摘要： A field effect semiconductor comprises a semiconductor layer having a surface, a first and a second semiconductor region in the semiconductor layer, which are arranged next to one another at the surface of the semiconductor layer, an insulating layer between the first semiconductor region and the second semiconductor region, a semiconductor strip on the surface of the semiconductor layer, which semiconductor strip overlaps the first semiconductor region and the second semiconductor region and adjoins these. A gate overlaps the semiconductor strip at least in the region of the insulating layer. A gate dielectric insulates the gate from the semiconductor strip the first semiconductor region and the second semiconductor region. The semiconductor strip and the gate being formed such that the semiconductor strip is electrically insulating at a first predetermined gate voltage and is electrically conductive at a second predetermined gate voltagero.
摘要翻译：场效应半导体包括在半导体层的表面上彼此相邻布置的半导体层中具有表面的第一和第二半导体区域的半导体层，在第一半导体区域和第二半导体区域之间的绝缘层半导体区域，半导体层的表面上的半导体条，该半导体条与第一半导体区域和第二半导体区域重叠，并与其邻接。至少在绝缘层的区域中，栅极与半导体条重叠。栅介质将栅极与半导体条绝缘在第一半导体区和第二半导体区之间。半导体条和栅极形成为使得半导体条以第一预定栅极电压电绝缘并且在第二预定栅极电压下导电。

42. 发明授权

US07266027B2 Integrated semiconduct memory with test circuit 有权
标题翻译：具有测试电路的集成半导体存储器
公开(公告)号：US07266027B2
公开(公告)日：2007-09-04
申请号：US11235540
申请日：2005-09-27
申请人： Ralf Schneider , Stephan Schröder , Manfred Pröll , Herbert Benzinger
发明人： Ralf Schneider , Stephan Schröder , Manfred Pröll , Herbert Benzinger
IPC分类号： G11C7/00
CPC分类号： G11C29/025 , G11C8/08 , G11C11/401 , G11C29/02 , G11C2029/1202
摘要： An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third controllable switch and to a second voltage potential via a respective second controllable switch. In order to test whether one of the word lines is connected to the first voltage potential via its respective first and third controllable switches, the one of the word lines is connected to a comparator circuit via the respective second controllable switch and a driver line. After the respective first and third controllable switches have been controlled into the on state, in a test operating state of the integrated semiconductor memory, the respective second controllable switch is controlled into the on state and a potential state on the word line is evaluated by the comparator circuit. The result of the evaluation is fed to an external data terminal by an evaluation signal.
摘要翻译：集成半导体存储器包括通过相应的第一可控开关和相应的第三可控开关连接到第一电压电位的字线，以及经由相应的第二可控开关连接到第二电压电位的字线。为了测试字线之一是否经由其相应的第一和第三可控开关连接到第一电压电位，所述字线之一经由相应的第二可控开关和驱动器线连接到比较器电路。在相应的第一和第三可控开关已经被控制为导通状态之后，在集成半导体存储器的测试操作状态下，将相应的第二可控开关控制在导通状态，并且字线上的电位状态由比较器电路。评估结果通过评估信号馈送到外部数据终端。

43. 发明授权

US07196537B2 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US07196537B2
公开(公告)日：2007-03-27
申请号：US11092963
申请日：2005-03-30
申请人： Aurel von Campenhausen , Joerg Vollrath , Ralf Schneider , Marcin Gnat
发明人： Aurel von Campenhausen , Joerg Vollrath , Ralf Schneider , Marcin Gnat
IPC分类号： G01R31/26
CPC分类号： G11C29/1201 , G01R31/275 , G01R31/2884 , G11C29/48 , G11C29/50 , G11C2029/5002
摘要： An integrated circuit includes a circuit component, a first control circuit and a switchable resistance network. An input voltage is fed to the circuit component on the input side. A control signal generated by the first control circuit is fed to the control terminal of the circuit component. With the switchable resistance network, the first resistance or the second resistance is connected between an output terminal of the circuit component and the output terminal of the integrated circuit to generate a voltage drop between the input side and the output terminal of the circuit component. The integrated circuit makes it possible to generate a current at the output terminal of the circuit component in a manner dependent on the control signal and the voltage dropped between the input side and the output terminal of the circuit component. Families of characteristic curves of transistors of an integrated circuit are determined by the integrated circuit.
摘要翻译：集成电路包括电路部件，第一控制电路和可切换电阻网络。输入电压被馈送到输入侧的电路部件。由第一控制电路产生的控制信号被馈送到电路部件的控制端。利用可切换电阻网络，第一电阻或第二电阻连接在电路部件的输出端和集成电路的输出端之间，以在电路部件的输入侧和输出端之间产生电压降。集成电路使得可以以取决于控制信号的方式在电路部件的输出端产生电流以及在电路部件的输入侧和输出端子之间落下的电压。集成电路的晶体管的特性曲线族由集成电路确定。

44. 发明申请

US20060278528A1 Method of effecting a signal readout on a gas-sensitive field-effect transistor 有权
标题翻译：在气敏场效应晶体管上实现信号读出的方法
公开(公告)号：US20060278528A1
公开(公告)日：2006-12-14
申请号：US11393371
申请日：2006-03-30
申请人： Maximilian Fleischer , Hans Meixner , Uwe Lampe , Roland Pohle , Ralf Schneider , Elfriede Simon
发明人： Maximilian Fleischer , Hans Meixner , Uwe Lampe , Roland Pohle , Ralf Schneider , Elfriede Simon
IPC分类号： G01N27/26 , H01L23/58
CPC分类号： G01N27/4143
摘要： Method of effecting a readout of a gas-sensitive field-effect transistor having an air gap between a gate electrode with a gas-sensitive layer and the readout transistor, in which a potential occurring on the gas-sensitive layer in the presence of a target gas is passed through a noncontacting floating gate electrode to the transistor, wherein the potential of a reference electrode, which together with the floating gate electrode generates a capacitance Cw, is tracked to the potential of the floating gate electrode in order to eliminate the capacitance Cw during the measurement.
摘要翻译：在具有气体敏感层的栅电极和读出晶体管之间进行气体敏感场效应晶体管的读出的方法，其中在存在目标的情况下在气敏层上发生电位气体通过非接触式浮栅电极到达晶体管，其中参考电极的电位与浮动栅电极一起产生电容C w i被追踪到浮置栅极的电位电极，以便在测量期间消除电容C 。

45. 发明授权

US07110310B2 RAM store and control method therefor 有权
标题翻译： RAM存储及其控制方法
公开(公告)号：US07110310B2
公开(公告)日：2006-09-19
申请号：US10762280
申请日：2004-01-23
申请人： Manfred Proell , Stephan Schroeder , Ralf Schneider , Joerg Kliewer
发明人： Manfred Proell , Stephan Schroeder , Ralf Schneider , Joerg Kliewer
IPC分类号： E03D1/02
CPC分类号： G11C7/18 , G11C7/12 , G11C11/4094 , G11C11/4097 , G11C2207/12
摘要： The invention relates to a RAM store having a shared SA structure, in which sense amplifiers (SA) arranged in SA strips (10) between two respective adjacent cell blocks are used by a plurality of bit line pairs (21, 22; 21–24) from the adjacent cell blocks and the bit line pairs (21, 22; 21–24) have respective charge equalization circuits individually associated with them for the purpose of performing charge equalization between the bit line halves of the bit line pairs (21, 22; 21–24) in a precharge phase, where a shorting transistor (30) is provided which, when prompted by a control signal (EQLx), connects the bit line halves (BLT, BLC) of the bit line pairs (21, 22; 21–24) which are in the precharge phase to one another. The shorting transistor (30) is arranged in or on the respective sense amplifier (SA) jointly for all bit line pairs (21, 22; 21–24) which can be connected to a repetitive sense amplifier (SA), and it can be switched by a separate shorting control signal (EQLx) via a dedicated control line (9).
摘要翻译：本发明涉及具有共享SA结构的RAM存储器，其中布置在两个相邻相邻单元块之间的SA带（10）中的读出放大器（SA）被多个位线对（21,22; 21-24 ）和位线对（21,22; 21-24）具有分别与它们相关联的电荷均衡电路，用于在位线对（21,22）的位线半部之间执行电荷均衡 ; 21-24），其中提供短路晶体管（30），当短路晶体管（30）由控制信号（EQLx）提示时，连接位线对（21,22）的位线半部（BLT，BLC） ; 21-24），它们彼此处于预充电阶段。短路晶体管（30）对于可以连接到重复读出放大器（SA）的所有位线对（21,22; 21-24）共同布置在相应的读出放大器（SA）中或上，通过专用控制线（9）通过单独的短路控制信号（EQLx）进行切换。

46. 发明授权

US06965535B2 Integrated semiconductor memory circuit and a method for operating the same 失效
标题翻译：集成半导体存储器电路及其操作方法
公开(公告)号：US06965535B2
公开(公告)日：2005-11-15
申请号：US10742761
申请日：2003-12-23
申请人： Manfred Proell , Stephan Schroeder , Ralf Schneider , Joerg Kliewer
发明人： Manfred Proell , Stephan Schroeder , Ralf Schneider , Joerg Kliewer
IPC分类号： G11C7/10 , G11C11/4096 , G11C11/4097 , G11C7/02
CPC分类号： G11C7/1048 , G11C11/4096 , G11C11/4097 , G11C2207/002
摘要： An integrated semiconductor memory includes a DRAM memory, in which primary sense amplifiers (SA) are coupled to a bit line (BL) of a respective cell block and can be connected to a common local data line (LDQ) by means of a respective assigned CSL switch in response to a CSL signal and in which an MDQ/LDQ switch arrangement connects a main data line (MDQ) to the local data line (LDQ) of a respective cell block in response to an MDQ/LDQ switch signal. In the case of the semiconductor memory, a control input of each CSL switch is connected to an AND element, which ANDs the CSL signal with the MDQ/LDQ switch signal and thereby activates the CSL switches only in cell blocks in which a word line has been activated.
摘要翻译：集成半导体存储器包括DRAM存储器，其中初级读出放大器（SA）耦合到各个单元块的位线（BL），并且可以通过相应的分配的连接到公共本地数据线（LDQ） CSL响应于CSL信号切换，并且其中MDQ / LDQ开关装置响应于MDQ / LDQ切换信号将主数据线（MDQ）连接到相应的单元块的本地数据线（LDQ）。在半导体存储器的情况下，每个CSL开关的控制输入连接到AND元件，AND元件将CSL信号与MDQ / LDQ开关信号进行AND运算，从而仅在字线具有的单元块中激活CSL开关被激活。

47. 发明授权

US06750670B2 Integrated test circuit 失效
标题翻译：集成测试电路
公开(公告)号：US06750670B2
公开(公告)日：2004-06-15
申请号：US10317933
申请日：2002-12-12
申请人： Thorsten Bucksch , Ralf Schneider
发明人： Thorsten Bucksch , Ralf Schneider
IPC分类号： G01R3102
CPC分类号： G01R31/3016
摘要： An integrated test circuit, as part of an integrated circuit, includes phase-shifted test signals fed through inputs A and B. These test signals are conducted through a plurality of cascaded delay elements, the advancing of the first test signal through the delay elements being held and evaluated by the second test signal.
摘要翻译：作为集成电路的一部分的集成测试电路包括通过输入A和B馈送的相移测试信号。这些测试信号通过多个级联延迟元件传导，第一测试信号通过延迟元件的前进是由第二测试信号进行保持和评估。

48. 发明授权

US6043691A Pulse shaper circuit 有权
标题翻译：脉冲整形电路
公开(公告)号：US6043691A
公开(公告)日：2000-03-28
申请号：US160862
申请日：1998-09-25
申请人： Bret Johnson , Ralf Schneider
发明人： Bret Johnson , Ralf Schneider
IPC分类号： H03K5/1252 , H03K17/16
CPC分类号： H03K5/1252
摘要： A pulse shaper circuit includes a buffer having an input, an output and two supply connections. A controllable first switch is connected between one of the supply connections and a first supply potential, a controllable second switch is connected between the other supply voltage connection and a second supply potential, a controllable third switch is connected between the output of the buffer and the first supply potential and a controllable fourth switch is connected between the output of the buffer and the second supply potential. A control device for the switches is connected to the output of the buffer and produces a first control pulse of a specific duration at the occurrence of first edges of a signal present at the output of the buffer and a second control pulse of a specific duration at the occurrence of second edges. The first control pulse changes over the first switch from the ON state to the OFF state and the fourth switch from the OFF state to the ON state. The second control pulse changes over the second switch from the ON state to the OFF state and the third switch from the OFF state to the ON state.
摘要翻译：脉冲整形器电路包括具有输入，输出和两个电源连接的缓冲器。一个可控的第一开关连接在一个电源连接点和一个第一电源电位之间，一个可控的第二开关连接在另一个电源电压连接和第二个电源电位之间，可控制的第三个开关连接在缓冲器的输出端和第一供电电位和可控第四开关连接在缓冲器的输出端与第二供电电位之间。用于开关的控制装置连接到缓冲器的输出，并且在存在于缓冲器的输出处的信号的第一边缘出现特定持续时间的第一控制脉冲和特定持续时间的第二控制脉冲发生第二个边缘。第一控制脉冲从第一开关从接通状态切换到断开状态，第四开关从断开状态转换到接通状态。第二控制脉冲将第二开关从ON状态切换到OFF状态，将第三开关从OFF状态切换到ON状态。

49. 发明授权

US5994936A RS flip-flop with enable inputs 有权
标题翻译： RS触发器使能输入
公开(公告)号：US5994936A
公开(公告)日：1999-11-30
申请号：US160880
申请日：1998-09-25
申请人： Bret Johnson , Ralf Schneider
发明人： Bret Johnson , Ralf Schneider
IPC分类号： H03K3/037 , H03K3/356
CPC分类号： H03K3/356113 , H03K3/037 , H03K3/356165
摘要： An RS flip-flop has an inverter, connected to an input terminal of the RS flip-flop, a NOR gate having an Enable-Set input, a NAND gate having an Enable-Reset input, and a first and a second transistor connected to the inverter. The outputs of the NOR and NAND gates are connected, via the gate paths of the first and second transistors, to the gate electrode of a third and a fourth transistor, respectively. The third and the fourth transistor are connected in series and form a holding element, whose common connection point is connected to the output of the inverter and to the output terminal of the flip-flop.
摘要翻译： RS触发器具有连接到RS触发器的输入端的反相器，具有使能置位输入的或非门，具有使能复位输入的与非门和与第一和第二晶体管连接的逆变器。 NOR和NAND门的输出分别经由第一和第二晶体管的栅极连接到第三和第四晶体管的栅电极。第三和第四晶体管串联连接并形成保持元件，其公共连接点连接到反相器的输出端和触发器的输出端。

50. 发明授权

US5660294A Rotating closure for a metallurgical vessel 失效
标题翻译：用于冶金容器的旋转盖
公开(公告)号：US5660294A
公开(公告)日：1997-08-26
申请号：US504829
申请日：1995-07-20
申请人： Ralf Schneider , Wolfram Jung , Hans-Joachim Paris
发明人： Ralf Schneider , Wolfram Jung , Hans-Joachim Paris
IPC分类号： B22D11/10 , B22D41/26 , B22D41/32 , B65D51/18 , B22D41/14
CPC分类号： B22D41/26
摘要： A rotating closure device for a runout opening in a base of a metallurgical vessel for preventing access of gases reacting with a melt. The device includes an upper closure plate (3) positioned at an end side of a drain block (1) and a lower closure plate (4) at the outlet (2). The upper closure plate (3) is provided with at least two through-holes for meeting at least two channels (7, 8) in the drain block (1), which channels (7, 8) extend parallel to an axis of rotation of the device. The lower closure plate (4) is provided with at least one through-hole for meeting at least one channel (6) in the outlet. The at least two chapels (7, 8) meet at least one channel (6) via a connection between the upper and lower closure plates (3, 4).
摘要翻译：一种用于在冶金容器的底部中用于防止与熔体反应的气体进入的跳动开口的旋转闭合装置。该装置包括位于排水块（1）的端侧的上封闭板（3）和出口（2）处的下封闭板（4）。上封闭板（3）设置有至少两个通孔，用于在排水块（1）中满足至少两个通道（7,8），该通道（7,8）平行于旋转轴线装置。下封闭板（4）设置有至少一个用于在出口处与至少一个通道（6）相通的通孔。所述至少两个教堂（7,8）经由所述上封闭板（3）和下封闭板（4）之间的连接件与至少一个通道（6）相交。

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