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41. 发明授权

US08924695B2 Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor 有权
标题翻译：条件ALU指令条件满足在读端口限制寄存器文件微处理器中的微指令之间的传播
公开(公告)号：US08924695B2
公开(公告)日：2014-12-30
申请号：US13333631
申请日：2011-12-21
申请人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30072 , G06F9/30123 , G06F9/30174
摘要： An architectural instruction instructs a microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result, determines whether the architectural condition flags satisfy the condition, and updates a non-architectural indicator to indicate whether the architectural condition flags satisfy the condition. To execute the first microinstruction, if the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags satisfy the condition, it updates the destination register with the result; otherwise, it updates the destination register with the current value of the destination register.
摘要翻译：架构指令指示微处理器对第一和第二源操作数执行操作以产生结果，并且只有在体系结构条件标志满足建筑指令中指定的条件时才将结果写入目的寄存器。硬件指令翻译器将架构指令转换为第一和第二微指令。为了执行第一微指令，执行流水线对源操作数执行操作以生成结果，确定架构条件标志是否满足条件，并更新非架构指示符以指示架构条件标志是否满足条件。为了执行第一微指令，如果由第一微指令更新的非架构指示符指示架构条件标志满足条件，则用结果更新目的寄存器; 否则，它将使用目标寄存器的当前值更新目标寄存器。

42. 发明授权

US08880857B2 Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor 有权
标题翻译：条件ALU指令在读端口限制寄存器文件微处理器中的微指令之前进行移位生成的进位标志传播
公开(公告)号：US08880857B2
公开(公告)日：2014-11-04
申请号：US13333572
申请日：2011-12-21
申请人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30094 , G06F9/30174
摘要： A microprocessor includes a hardware instruction translator that translates an architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the shift operation on the first source operand to generate the first result and a carry flag value and updates a non-architectural carry flag with the generated carry flag value. To execute the second microinstruction, it performs the second operation on the first result and the second operand to generate the second result and new condition flag values based on the second result. If a architectural condition flags satisfy the condition, it updates the architectural carry flag with the non-architectural carry flag value and updates at least one of the other architectural condition flags with the corresponding generated new condition flag values; otherwise, it updates the architectural condition flags with the current value of the architectural condition flags.
摘要翻译：微处理器包括将架构指令转换成第一和第二微指令的硬件指令转换器。为了执行第一微指令，执行流水线对第一源操作数执行移位操作以产生第一结果和进位标志值，并且利用所生成的进位标志值更新非架构进位标志。为了执行第二微指令，它对第一结果和第二操作数执行第二操作，以基于第二结果产生第二结果和新条件标志值。如果架构条件标志满足条件，则使用非架构进位标志值来更新架构进位标志，并用对应的生成的新条件标志值来更新其他架构状态标志中的至少一个; 否则，它使用架构条件标志的当前值更新架构条件标志。

43. 发明授权

US08880851B2 Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline 有权
标题翻译：通过硬件转换执行X86 ISA和arm ISA机器语言程序指令的微处理器由通用执行管道执行的微指令
公开(公告)号：US08880851B2
公开(公告)日：2014-11-04
申请号：US13224310
申请日：2011-09-01
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/30 , G06F9/26
CPC分类号： G06F9/441 , G06F9/265 , G06F9/30043 , G06F9/30072 , G06F9/30076 , G06F9/30105 , G06F9/30123 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/3802 , G06F9/4401 , G06F9/4403 , G06F15/82
摘要： A microprocessor includes a hardware instruction translator that translates x86 ISA and ARM ISA machine language program instructions into microinstructions, which are encoded in a distinct manner from the x86 and ARM instructions. An execution pipeline executes the microinstructions to generate x86/ARM-defined results. The microinstructions are distinct from the results generated by the execution of the microinstructions by the execution pipeline. The translator directly provides the microinstructions to the execution pipeline for execution. Each time the microprocessor performs one of the x86 ISA and ARM ISA instructions, the translator translates it into the microinstructions. An indicator indicates either x86 or ARM as a boot ISA. After reset, the microprocessor initializes its architectural state, fetches its first instructions from a reset address, and translates them all as defined by the boot ISA. An instruction cache caches the x86 and ARM instructions and provides them to the translator.
摘要翻译：微处理器包括硬件指令转换器，将x86 ISA和ARM ISA机器语言程序指令转换为微指令，它们以不同于x86和ARM指令的方式进行编码。执行流水线执行微指令以生成x86 / ARM定义的结果。微指令与由执行管道执行微指令生成的结果不同。翻译器直接向执行管道提供微指令以供执行。每当微处理器执行x86 ISA和ARM ISA指令之一时，翻译器将其转换为微指令。指示符指示x86或ARM作为引导ISA。复位后，微处理器初始化其架构状态，从复位地址获取其第一条指令，并按照引导ISA定义将其全部转换。指令缓存缓存x86和ARM指令，并将其提供给翻译器。

44. 发明授权

US08838924B2 Microprocessor having internal secure memory 有权
标题翻译：微处理器具有内部安全存储器
公开(公告)号：US08838924B2
公开(公告)日：2014-09-16
申请号：US12263143
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F12/00 , G06F21/72 , G06F21/70
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/12 , G06F21/14 , G06F21/554 , G06F21/70 , G06F21/71 , G06F21/73 , G06F21/74 , G06F21/75 , G06F21/82
摘要： An apparatus providing for a secure execution environment. The apparatus includes a microprocessor that is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The microprocessor has a non-secure memory and a secure volatile memory. The non-secure memory is configured to store portions of the non-secure application programs for execution by the microprocessor, where the non-secure memory is observable and accessible by the non-secure application programs and by system bus resources within the microprocessor. The secure volatile memory is configured to store the secure application program for execution by the microprocessor, where the secure volatile memory is isolated from the non-secure application programs and the system bus resources within the microprocessor. The secure application program is decrypted using a processor unique key and is written to the secure volatile memory.
摘要翻译：一种提供安全执行环境的设备。该装置包括被配置为执行非安全应用程序和安全应用程序的微处理器，其中通过系统总线从系统存储器访问非安全应用程序。微处理器具有非安全存储器和安全易失性存储器。非安全存储器被配置为存储用于由微处理器执行的非安全应用程序的部分，其中非安全存储器是可观察的并且可由非安全应用程序和微处理器内的系统总线资源访问。安全易失性存储器被配置为存储用于由微处理器执行的安全应用程序，其中安全易失性存储器与非安全应用程序和微处理器内的系统总线资源隔离。安全应用程序使用处理器唯一密钥解密，并被写入安全易失性存储器。

45. 发明授权

US08316243B2 Apparatus and method for generating unpredictable processor-unique serial number for use as an encryption key 有权
标题翻译：用于产生用于加密密钥的不可预测的处理器唯一序列号的装置和方法
公开(公告)号：US08316243B2
公开(公告)日：2012-11-20
申请号：US12781124
申请日：2010-05-17
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F21/00
CPC分类号： G06F21/73 , G09C1/00 , H04L9/0631 , H04L9/0866 , H04L9/0894 , H04L2209/12
摘要： A microprocessor includes a manufacturing ID that is stored in the microprocessor during manufacture thereof in a non-volatile manner. The manufacturing ID is unique to the microprocessor. The microprocessor also includes a secret encryption key that is stored internally within the microprocessor and unreadable externally from the microprocessor. The microprocessor also includes an AES encryption engine, coupled to receive the manufacturing ID and the secret encryption key, configured to encrypt the manufacturing ID using the secret encryption key to generate an unpredictable key that is unique to the microprocessor.
摘要翻译：微处理器包括以非易失性方式在其制造期间存储在微处理器中的制造ID。制造ID是微处理器独有的。微处理器还包括秘密加密密钥，该秘密加密密钥存储在微处理器的内部并且不能从微处理器外部读出。微处理器还包括耦合以接收制造ID和秘密加密密钥的AES加密引擎，其配置为使用秘密加密密钥加密制造ID，以产生微处理器唯一的不可预测的密钥。

46. 发明申请

US20120260073A1 EMULATION OF EXECUTION MODE BANKED REGISTERS 审中-公开
标题翻译：执行模式银行登记的模拟
公开(公告)号：US20120260073A1
公开(公告)日：2012-10-11
申请号：US13413300
申请日：2012-03-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F9/302
CPC分类号： G06F9/30189 , G06F9/30043 , G06F9/30076 , G06F9/30094 , G06F9/30123 , G06F9/30174 , G06F9/321 , G06F9/3802
摘要： A microprocessor includes processor modes comprising a user mode and a plurality of exception modes. An execution unit performs arithmetic operations on operands specified by program instructions. A first set of storage elements holds a first subset of the operands and provides them to the execution unit coupled thereto. A second set of storage elements associated with each of the modes hold a second subset of the operands and are incapable of directly providing the second operand subset to the execution unit. To enter a new mode from a current mode, logic saves the first operand subset held in the first set of storage elements to the second set of storage elements associated with the current mode and restores to the first set of storage elements the second operand subset held in the second set of storage elements associated with the new mode.
摘要翻译：微处理器包括包括用户模式和多个异常模式的处理器模式。执行单元对程序指令指定的操作数执行算术运算。第一组存储元件保存操作数的第一子集，并将它们提供给耦合到其的执行单元。与每种模式相关联的第二组存储元件容纳操作数的第二子集，并且不能将第二操作数子集直接提供给执行单元。为了从当前模式进入新模式，逻辑将保存在第一组存储元件中的第一操作数子集保存到与当前模式相关联的第二组存储元件，并将第二操作数子集保存到第一组存储元件在与新模式相关联的第二组存储元件中。

47. 发明申请

US20120260064A1 HETEROGENEOUS ISA MICROPROCESSOR WITH SHARED HARDWARE ISA REGISTERS 有权
标题翻译：具有共享硬件ISA寄存器的异质ISA微处理器
公开(公告)号：US20120260064A1
公开(公告)日：2012-10-11
申请号：US13412888
申请日：2012-03-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/30123 , G06F9/30076 , G06F9/3013 , G06F9/30174 , G06F9/30181 , G06F9/30189 , G06F9/4403
摘要： A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program and a plurality of hardware registers. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, the plurality of hardware registers store x86 ISA architectural state; when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, the plurality of hardware registers store ARM ISA architectural state.
摘要翻译：能够运行x86指令集架构（ISA）机器语言程序和高级RISC机器（ARM）的微处理器ISA机器语言程序包括指示微处理器当前是否正在获取x86 ISA或ARM ISA机器语言程序的指令的模式指示器和多个硬件寄存器。当模式指示灯指示微处理器当前正在获取x86 ISA机器语言程序指令时，多个硬件寄存器存储x86 ISA架构状态; 当模式指示灯指示微处理器当前正在获取ARM ISA机器语言程序指令时，多个硬件寄存器存储ARM ISA架构状态。

48. 发明授权

US08131984B2 Pipelined microprocessor with fast conditional branch instructions based on static serializing instruction state 有权
标题翻译：流水线微处理器，具有基于静态串行化指令状态的快速条件分支指令
公开(公告)号：US08131984B2
公开(公告)日：2012-03-06
申请号：US12481499
申请日：2009-06-09
申请人： G. Glenn Henry , Terry Parks , Brent Bean
发明人： G. Glenn Henry , Terry Parks , Brent Bean
IPC分类号： G06F9/32
CPC分类号： G06F9/30058 , G06F9/3867
摘要： A microprocessor includes a control register that stores a control value that affects operation of the microprocessor. An instruction set architecture includes a conditional branch instruction that specifies a branch condition based on the control value stored in the control register, and a serializing instruction that updates the control value in the control register. The microprocessor completes all modifications to flags, registers, and memory by instructions previous to the serializing instruction and to drain all buffered writes to memory before it fetches and executes the next instruction after the serializing instruction. Execution units update the control value in the control register in response to the serializing instruction. A fetch unit fetches, decodes, and unconditionally correctly resolves and retires the conditional branch instruction based on the control value stored in the control register rather than dispatching the conditional branch instruction to the execution units to be resolved.
摘要翻译：微处理器包括控制寄存器，其存储影响微处理器的操作的控制值。指令集架构包括基于存储在控制寄存器中的控制值来指定分支条件的条件转移指令，以及更新控制寄存器中的控制值的串行化指令。微处理器通过串行化指令之前的指令完成对标志，寄存器和存储器的所有修改，并在串行化指令之前取出并执行下一条指令，将所有缓冲写入消耗到存储器中。响应串行化指令，执行单元更新控制寄存器中的控制值。取出单元基于存储在控制寄存器中的控制值来取得，解码和无条件地正确地解析和退出条件转移指令，而不是将条件转移指令分派到要解析的执行单元。

49. 发明授权

US07975132B2 Apparatus and method for fast correct resolution of call and return instructions using multiple call/return stacks in the presence of speculative conditional instruction execution in a pipelined microprocessor 有权
标题翻译：在存在流水线微处理器中的推测性条件指令执行的情况下，使用多个调用/返回堆栈快速正确解析呼叫和返回指令的装置和方法
公开(公告)号：US07975132B2
公开(公告)日：2011-07-05
申请号：US12481074
申请日：2009-06-09
申请人： Brent Bean , Terry Parks , G. Glenn Henry
发明人： Brent Bean , Terry Parks , G. Glenn Henry
IPC分类号： G06F9/38
CPC分类号： G06F9/30054 , G06F9/3806 , G06F9/3844
摘要： A microprocessor having a plurality of call/return stacks (CRS) correctly resolves a call or return instruction rather than issuing the instruction to execution units of the microprocessor to be resolved. The microprocessor fetches a call or return instruction and determines whether the instruction is the first call or return instruction fetched after fetching a conditional branch instruction that has yet to be resolved. The microprocessor copies the contents of a current CRS to another CRS and designates the other CRS as the current CRS, if the state exists. The microprocessor pushes the address of the next sequential instruction following the call instruction onto the current CRS and fetches an instruction at the call instruction target address if the instruction is a call instruction. The microprocessor pops a second return address from the current CRS and fetches an instruction at the second return address, if the instruction is a return instruction.
摘要翻译：具有多个呼叫/返回栈（CRS）的微处理器正确地解析了呼叫或返回指令，而不是向要解析的微处理器的执行单元发出指令。微处理器获取一个调用或返回指令，并确定该指令是否是在获取尚未解决的条件分支指令之后获取的第一个调用或返回指令。如果状态存在，则微处理器将当前CRS的内容复制到另一个CRS，并将其他CRS指定为当前CRS。如果指令是呼叫指令，微处理器将呼叫指令之后的下一个顺序指令的地址推送到当前CRS上，并在调用指令目标地址处取指令。如果指令是返回指令，则微处理器从当前CRS中弹出第二个返回地址，并在第二个返回地址处获取指令。

50. 发明申请

US20110035599A1 APPARATUS AND METHOD FOR GENERATING UNPREDICTABLE PROCESSOR-UNIQUE SERIAL NUMBER FOR USE AS AN ENCRYPTION KEY 有权
标题翻译：用于生成用于加密密钥的不可预测的处理器 - 唯一序列号的装置和方法
公开(公告)号：US20110035599A1
公开(公告)日：2011-02-10
申请号：US12781124
申请日：2010-05-17
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F21/00 , G06F12/14 , H04L9/00
CPC分类号： G06F21/73 , G09C1/00 , H04L9/0631 , H04L9/0866 , H04L9/0894 , H04L2209/12
摘要： A microprocessor includes a manufacturing ID that is stored in the microprocessor during manufacture thereof in a non-volatile manner. The manufacturing ID is unique to the microprocessor. The microprocessor also includes a secret encryption key that is stored internally within the microprocessor and unreadable externally from the microprocessor. The microprocessor also includes an AES encryption engine, coupled to receive the manufacturing ID and the secret encryption key, configured to encrypt the manufacturing ID using the secret encryption key to generate an unpredictable key that is unique to the microprocessor.
摘要翻译：微处理器包括以非易失性方式在其制造期间存储在微处理器中的制造ID。制造ID是微处理器独有的。微处理器还包括秘密加密密钥，该秘密加密密钥存储在微处理器的内部并且不能从微处理器外部读出。微处理器还包括耦合以接收制造ID和秘密加密密钥的AES加密引擎，其配置为使用秘密加密密钥加密制造ID，以产生微处理器唯一的不可预测的密钥。

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