会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 47. 发明授权
    • Full virtualization of resources across an IP interconnect using page frame table
    • 使用页面框架表在IP互连中完全虚拟化资源
    • US07904693B2
    • 2011-03-08
    • US12024773
    • 2008-02-01
    • Ravi K. ArimilliClaude BassoJean L. CalvignacPiyush ChaudharyEdward J. Seminaro
    • Ravi K. ArimilliClaude BassoJean L. CalvignacPiyush ChaudharyEdward J. Seminaro
    • G06F12/10
    • G06F12/10G06F12/1081H04L29/12018H04L61/10
    • An addressing model is provided where devices, including I/O devices, are addressed with internet protocol (IP) addresses, which are considered part of the virtual address space. A task, such as an application, may be assigned an effective address range, which corresponds to addresses in the virtual address space. The virtual address space is expanded to include Internet protocol addresses. Thus, the page frame tables are also modified to include entries for IP addresses and additional properties for devices and I/O. Thus, a processing element, such as an I/O adapter or even a printer, for example, may also be addressed using IP addresses without the need for library calls, device drivers, pinning memory, and so forth. This addressing model also provides full virtualization of resources across an IP interconnect, allowing a process to access an I/O device across a network.
    • 提供了一种寻址模型,其中包括I / O设备在内的设备通过互联网协议(IP)地址进行寻址,这些地址被认为是虚拟地址空间的一部分。 可以为任务(例如应用程序)分配与虚拟地址空间中的地址对应的有效地址范围。 虚拟地址空间被扩展为包括互联网协议地址。 因此,页框表也被修改为包括用于设备和I / O的IP地址和附加属性的条目。 因此,例如,诸如I / O适配器或甚至打印机的处理元件也可以使用IP地址来寻址,而不需要库调用,设备驱动器,固定存储器等。 该寻址模型还可以跨IP互连提供资源的完全虚拟化,从而允许进程通过网络访问I / O设备。
    • 49. 发明申请
    • Method and Apparatus for Supporting Multiple High Bandwidth I/O Controllers on a Single Chip
    • 在单芯片上支持多个高带宽I / O控制器的方法和装置
    • US20100122011A1
    • 2010-05-13
    • US12270569
    • 2008-11-13
    • Ravi K. ArimilliClaude BassoJean L. CalvignacDaniel M. DrepsEdward J. Seminaro
    • Ravi K. ArimilliClaude BassoJean L. CalvignacDaniel M. DrepsEdward J. Seminaro
    • G06F13/00
    • G06F13/385
    • An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage. Each physical interface may be programmatically connected to a selected interface controller, such as a memory controller, a PCI Express controller, or an Ethernet controller, for example. A plurality of such controllers may be connected to a switch within the processor design, with the switch also being connected to each physical interface macro. Thus, the physical interface macros may be programmatically connected to a subset of the plurality of controllers.
    • 集成处理器设计包括支持异质电气特性的物理接口宏。 处理器设计包括多个处理核心和多个物理接口以连接到存储器接口,用于输入/输出的外围组件互连快速(PCI Express或PCIe)接口,用于网络通信的以太网接口和/或 串行连接SCSI(SAS)接口进行存储。 每个物理接口可以以编程方式连接到例如存储器控制器,PCI Express控制器或以太网控制器等所选择的接口控制器。 多个这样的控制器可以连接到处理器设计中的开关,开关也连接到每个物理接口宏。 因此,物理接口宏可以以编程方式连接到多个控制器的子集。