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41. 发明授权

US5699315A Data processing with energy-efficient, multi-divided module memory architectures 失效
标题翻译：数据处理与节能，多分区模块存储架构
公开(公告)号：US5699315A
公开(公告)日：1997-12-16
申请号：US739239
申请日：1996-10-29
申请人： Uming Ko
发明人： Uming Ko
IPC分类号： G11C7/00 , G11C8/10
CPC分类号： G11C7/00 , G11C8/10
摘要： A memory architecture (11,12) includes an address bus and a plurality of address decoders (15). Each address decoder has an input which is selectively connectable to and disconnectable from the address bus.
摘要翻译：存储器架构（11,12）包括地址总线和多个地址解码器（15）。每个地址解码器具有可选择地连接到地址总线并可与地址总线断开的输入。

42. 发明授权

US5612636A Short circuit power optimization for CMOS circuits 失效
标题翻译： CMOS电路的短路功率优化
公开(公告)号：US5612636A
公开(公告)日：1997-03-18
申请号：US375147
申请日：1995-01-19
申请人： Uming Ko
发明人： Uming Ko
IPC分类号： H03K19/00 , H03K19/0948 , G06F15/00
CPC分类号： H03K19/0013 , G06F2217/78
摘要： An electronic circuit is constructed from a plurality of logic gates, each logic gate including a logic input, a logic output and a pair of power supply inputs, and each logic gate being operable to permit short circuit current to flow between the power supply inputs thereof during a logic level transition at the logic input thereof. A first logic gate (L) and a second logic gate (D) are provided with the output of the second logic gate connected to the input of the first logic gate, and the drive strength of the second logic gate is selected as a function of the short circuit current permitted by the first logic gate.
摘要翻译：电子电路由多个逻辑门构成，每个逻辑门包括逻辑输入，逻辑输出和一对电源输入，每个逻辑门可操作以允许短路电流在其电源输入之间流动在其逻辑输入处的逻辑电平转换期间。第一逻辑门（L）和第二逻辑门（D）设置有连接到第一逻辑门的输入的第二逻辑门的输出，并且第二逻辑门的驱动强度被选择为第一逻辑门允许的短路电流。

43. 发明授权

US5552726A High resolution digital phase locked loop with automatic recovery logic 失效
标题翻译：具有自动恢复逻辑的高分辨率数字锁相环
公开(公告)号：US5552726A
公开(公告)日：1996-09-03
申请号：US58168
申请日：1993-05-05
申请人： Shannon A. Wichman , Uming Ko
发明人： Shannon A. Wichman , Uming Ko
IPC分类号： H03L7/081 , H04L7/033 , H04L7/08
CPC分类号： H03L7/0814 , H03L7/0818
摘要： A phase locked loop circuit 11 includes a phase detection circuit 12, a means for phase adjustment, and a recovery circuit 18. The phase detection circuit 12 monitors the phase relationship between two signals and communicates the phase relationship to the phase adjustment means. The phase adjustment means provides appropriate delay to one of the signals to synchronize the two signals. The recover circuit 18 monitors the phase adjustment means for synchronization failures and provides appropriate notice to the phase adjustment means. The phase locked loop circuit 11 provides improved phase jitter resolution through the phase adjustment means. The circuit provides failure identification and correction through the recovery circuit resulting in improved phase locked loop circuit performance and reliability.
摘要翻译：锁相环电路11包括相位检测电路12，相位调整装置和恢复电路18.相位检测电路12监视两个信号之间的相位关系，并将相位关系传送给相位调整装置。相位调整装置为一个信号提供适当的延迟以使两个信号同步。恢复电路18监视相位调整装置的同步故障，并向相位调整装置提供适当的通知。锁相环电路11通过相位调整装置提供改进的相位抖动分辨率。该电路通过恢复电路提供故障识别和校正，从而改善了锁相环电路的性能和可靠性。

44. 发明授权

US5475320A Data processing with a self-timed approach to spurious transitions 失效
标题翻译：数据处理采用自定时方式进行虚假转换
公开(公告)号：US5475320A
公开(公告)日：1995-12-12
申请号：US289073
申请日：1994-08-11
申请人： Uming Ko
发明人： Uming Ko
IPC分类号： H03K5/1534 , H03K19/003
CPC分类号： H03K5/1534
摘要： A digital electronic device includes a digital circuit responsive to a logic transition at an input thereof to produce at an output thereof a spurious logic transition ultimately followed by a stable logic level. A transition detector produces a detection signal in response to the logic transition at the digital circuit input, the transition detector including a latch circuit having an output for producing the detection signal. A self-timed circuit receives the detection signal and, after delaying for a suitable time, produces a done signal. A switching circuit is responsive to the done signal to connect the digital circuit output to a selected logic node.
摘要翻译：数字电子设备包括响应于其输入处的逻辑转换的数字电路，以在其输出端产生寄生逻辑转变，最终后跟稳定的逻辑电平。转换检测器响应于数字电路输入处的逻辑转换而产生检测信号，转换检测器包括具有用于产生检测信号的输出的锁存电路。自定时电路接收检测信号，并且在延迟合适的时间之后产生完成的信号。开关电路响应于完成信号将数字电路输出连接到选定的逻辑节点。

45. 发明授权

US07519925B2 Integrated circuit with dynamically controlled voltage supply 有权
标题翻译：具有动态控制电压供应的集成电路
公开(公告)号：US07519925B2
公开(公告)日：2009-04-14
申请号：US11139452
申请日：2005-05-27
申请人： Sami Issa , Uming Ko , David Scott
发明人： Sami Issa , Uming Ko , David Scott
IPC分类号： G06F17/50
CPC分类号： G01R31/3004 , G06F17/5063
摘要： An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry (221) for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry (26) for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability. In selected instances, the circuitry for adjusting adjusts the voltage supplied by the voltage supply to be a voltage greater than the predetermined voltage operating limit while still complying with the predicted lifespan.
摘要翻译：电子系统（10）。该系统包括用于从电压源接收系统电压的电路（P1）。系统还包括响应系统电压的用于提供数据处理功能的电路（141）。用于提供数据处理功能的电路包括关键路径（CP1），并且关键路径包括多个晶体管。多个晶体管中的至少一些晶体管具有对应于预测寿命的相应的预定电压工作极限。该系统还包括用于指示关键路径的操作速度的潜在能力的电路（221）。该系统还包括用于将系统电压耦合到关键路径的电路（CB）。最后，该系统还包括用于响应于用于指示潜在能力的电路来调节由电压源提供的系统电压的电路（26）。在选择的情况下，用于调整的电路将电压供应提供的电压调整为大于预定电压工作极限的电压，同时仍然符合预期的使用寿命。

46. 发明申请

US20070290270A1 Performance and Area Scalable Cell Architecture Technology 有权
标题翻译：性能和面积可扩展单元架构技术
公开(公告)号：US20070290270A1
公开(公告)日：2007-12-20
申请号：US11745250
申请日：2007-05-07
申请人： Uming Ko , Dharin Shah , Senthil Sundaramoorthy , Girishankar Gurumurthy , Sumanth Gururajarao , Rolf Lagerquist , Clive Bittlestone
发明人： Uming Ko , Dharin Shah , Senthil Sundaramoorthy , Girishankar Gurumurthy , Sumanth Gururajarao , Rolf Lagerquist , Clive Bittlestone
IPC分类号： H01L29/768 , G06F17/50
CPC分类号： G06F17/5072 , H01L27/0207 , H01L27/11807
摘要： An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.
摘要翻译：集成电路。集成电路包括具有排列成行的布局的区域。每行可由一对行边界定义。集成电路还包括多个单元，包括第一组单元。第一组单元中的每个单元跨过至少两行并且包括具有跨越行边界中的一个的源极/漏极区域的PMOS晶体管和具有跨越行边界之一的源极/漏极区域的NMOS晶体管。

47. 发明授权

US07282905B2 System and method for IDDQ measurement in system on a chip (SOC) design 有权
标题翻译：系统芯片（SOC）设计中IDDQ测量的系统和方法
公开(公告)号：US07282905B2
公开(公告)日：2007-10-16
申请号：US11010135
申请日：2004-12-10
申请人： Wei Chen , Hugh T. Mair , Uming Ko , David B. Scott
发明人： Wei Chen , Hugh T. Mair , Uming Ko , David B. Scott
IPC分类号： G01R31/26
CPC分类号： G01R31/3008 , G01R31/3012
摘要： System and method for detecting transistor failure in large-scale integrated circuits by measuring IDDQ. A preferred embodiment comprises a switch structure for an integrated circuit made up of a plurality of main switches (such as main switch 410) selectively coupling a power sub-domain to a power source pin, a plurality of pi-switches (such as pi-switch 415) selectively coupling pairs of power sub-domains, and a plurality of IDDQ switches (such as IDDQ switch 425) selectively coupling the power sub-domains to a VIDDQ pin. The pi-switches can decouple the power sub-domains while the IDDQ switches can enable the measurement of the quiescent current in the power sub-domains. The use of pi-switches and IDDQ switches can permit the measurement of the quiescent current in the power sub-domains without requiring the use of isolation buffers and needed to powering on and off the integrated circuit between current measurements in the different power sub-domains.
摘要翻译：通过测量IDDQ来检测大型集成电路中的晶体管故障的系统和方法。优选实施例包括由多个选择性地将电源子域耦合到电源引脚的多个主开关（例如主开关410）构成的集成电路的开关结构，多个pi开关（例如，开关415）选择性地耦合功率子域对，以及选择性地将功率子域耦合到VIDDQ引脚的多个IDDQ开关（例如IDDQ开关425）。 pi开关可以对功率子域进行去耦，而IDDQ开关可以测量电源子域中的静态电流。 pi开关和IDDQ开关的使用可以允许测量电源子域中的静态电流，而不需要使用隔离缓冲器，并且需要在不同功率子域中的电流测量之间为集成电路供电和关断。

48. 发明申请

US20050273742A1 Integrated circuit with dynamically controlled voltage supply 有权
标题翻译：具有动态控制电压供应的集成电路
公开(公告)号：US20050273742A1
公开(公告)日：2005-12-08
申请号：US11139452
申请日：2005-05-27
申请人： Sami Issa , Uming Ko , David Scott
发明人： Sami Issa , Uming Ko , David Scott
IPC分类号： G06F9/45
CPC分类号： G01R31/3004 , G06F17/5063
摘要： An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry (221) for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry (26) for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability. In selected instances, the circuitry for adjusting adjusts the voltage supplied by the voltage supply to be a voltage greater than the predetermined voltage operating limit while still complying with the predicted lifespan.
摘要翻译：电子系统（10）。该系统包括用于从电压源接收系统电压的电路（P 1 SUB）。该系统还包括响应于系统电压的用于提供数据处理功能的电路（14 1 1）。用于提供数据处理功能的电路包括关键路径（CP <1> 1），并且关键路径包括多个晶体管。多个晶体管中的至少一些晶体管具有对应于预测寿命的相应的预定电压工作极限。该系统还包括用于指示关键路径的操作速度的潜在能力的电路（22I 1）。该系统还包括用于将系统电压耦合到关键路径的电路（CB）。最后，该系统还包括用于响应于用于指示潜在能力的电路来调节由电压源提供的系统电压的电路（26）。在选择的情况下，用于调整的电路将电压供应提供的电压调整为大于预定电压工作极限的电压，同时仍然符合预期的使用寿命。

49. 发明授权

US6151262A Apparatus, system and method for control of speed of operation and power consumption of a memory 有权
标题翻译：用于控制存储器的操作速度和功耗的装置，系统和方法
公开(公告)号：US6151262A
公开(公告)日：2000-11-21
申请号：US426960
申请日：1999-10-26
申请人： Baher S. Haroun , Uming Ko
发明人： Baher S. Haroun , Uming Ko
IPC分类号： G11C7/16 , G11C7/22 , H04M1/73 , G11C7/00
CPC分类号： G11C7/16 , G11C7/22
摘要： This invention concerns power consumption control of memory having a fully powered state and at least one lower power state. The invention changes the memory to the fully powered state upon receipt of a memory access request. This memory access request is serviced in the fully powered state. The memory is returned to a lower power state after expiration of a grace period following a last memory access request. This grace period can be measured by a predetermined time or a predetermined number of memory access requests or a combination of these factors. The predetermined time may be fixed in manufacture or programmable in operation via a control register or data stored in a predetermined set of address locations within the address space of the memory. This invention is useful in portable electronic devices such as wireless telephones.
摘要翻译：本发明涉及具有完全供电状态和至少一个较低功率状态的存储器的功耗控制。本发明在接收到存储器访问请求时将存储器改变为完全供电状态。该存储器访问请求在完全供电状态下被服务。在最后一次存储器访问请求之后的宽限期期满之后，存储器返回到较低功率状态。可以通过预定时间或预定数量的存储器访问请求或这些因素的组合来测量该宽限期。预定时间可以通过控制寄存器或存储在存储器的地址空间内的预定的一组地址位置中的数据在制造中固定或在操作中可编程。本发明在诸如无线电话的便携式电子设备中是有用的。

50. 发明授权

US5784291A CPU, memory controller, bus bridge integrated circuits, layout structures, system and methods 失效
标题翻译： CPU，存储控制器，总线桥式集成电路，布局结构，系统和方法
公开(公告)号：US5784291A
公开(公告)日：1998-07-21
申请号：US705034
申请日：1996-08-29
申请人： Ian Chen , Uming Ko
发明人： Ian Chen , Uming Ko
IPC分类号： G06F15/78 , G06F1/00 , G06F9/00
CPC分类号： G06F15/78
摘要： An integrated circuit includes a single chip (102) that has a microprocessor (702), a memory controller unit (718), an internal bus (714) connecting the microprocessor (702) and the memory controller unit (718), and an external bus to internal bus interface circuit (716). The microprocessor (102) occupies a substantially rectangular region on a substrate (802). The memory controller unit (718) occupies a first strip along one side of the microprocessor unit (702) accessible via the bond pads broadside to the first strip. Other circuits, systems, and methods are disclosed.
摘要翻译：集成电路包括具有微处理器（702），存储器控制器单元（718），连接微处理器（702）和存储器控制器单元（718）的内部总线（714））的单个芯片（102）总线到内部总线接口电路（716）。微处理器（102）在衬底（802）上占据基本矩形的区域。存储器控制器单元（718）占据沿着微处理器单元（702）的一侧的第一条带，可通过接合焊盘宽边到第一条带。公开了其他电路，系统和方法。

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