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41. 发明申请

US20080093628A1 Methods of Forming Semiconductor Devices Having Multiple Channel MOS Transistors and Related Intermediate Structures 有权
标题翻译：形成具有多通道MOS晶体管和相关中间结构的半导体器件的方法
公开(公告)号：US20080093628A1
公开(公告)日：2008-04-24
申请号：US11941656
申请日：2007-11-16
申请人： Sung-Young Lee , Sung-Min Kim , Dong-Gun Park , Chang-Woo Oh , Eun-Jung Yun
发明人： Sung-Young Lee , Sung-Min Kim , Dong-Gun Park , Chang-Woo Oh , Eun-Jung Yun
IPC分类号： H01L29/778
CPC分类号： H01L29/66484 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/7831 , H01L29/78696
摘要： In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched using the hard mask as an etching mask to expose a surface of the substrate. The etched preliminary active pattern is trimmed to form an active channel pattern having a width less than a lower width of the hard mask. Source/drain layers are formed on exposed side faces of the active channel pattern and the surface. The gate layers are selectively etched to form tunnels. A gate encloses the active channel pattern and filling the tunnels. Related intermediate structures are also disclosed.
摘要翻译：在制造半导体器件的方法中，在衬底上形成包括栅极层和沟道层的初步有源图案。交替层叠栅极层和沟道层。在初步活性图案上形成硬掩模。使用硬掩模作为蚀刻掩模来部分蚀刻预活性图案以暴露基板的表面。蚀刻的预活化图案被修整以形成宽度小于硬掩模的较低宽度的有源通道图案。源极/漏极层形成在有源沟道图案和表面的暴露侧面上。选择性地蚀刻栅极层以形成隧道。一个门包围有源通道模式并填充隧道。还公开了相关的中间结构。

42. 发明授权

US07316968B2 Methods of forming semiconductor devices having multiple channel MOS transistors 有权
标题翻译：形成具有多通道MOS晶体管的半导体器件的方法
公开(公告)号：US07316968B2
公开(公告)日：2008-01-08
申请号：US10974410
申请日：2004-10-27
申请人： Sung-Young Lee , Sung-Min Kim , Dong-Gun Park , Chang-Woo Oh , Eun-Jung Yun
发明人： Sung-Young Lee , Sung-Min Kim , Dong-Gun Park , Chang-Woo Oh , Eun-Jung Yun
IPC分类号： H01L21/00
CPC分类号： H01L29/66484 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/7831 , H01L29/78696
摘要： In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is partially etched using the hard mask as an etching mask to expose a surface of the substrate. The etched preliminary active pattern is trimmed to form an active channel pattern having a width less than a lower width of the hard mask. Source/drain layers are formed on exposed side faces of the active channel pattern and the surface. The gate layers are selectively etched to form tunnels. A gate encloses the active channel pattern and filling the tunnels. Related intermediate structures are also disclosed.
摘要翻译：在制造半导体器件的方法中，在衬底上形成包括栅极层和沟道层的初步有源图案。交替层叠栅极层和沟道层。在初步活性图案上形成硬掩模。使用硬掩模作为蚀刻掩模来部分蚀刻预活性图案以暴露基板的表面。蚀刻的预活化图案被修整以形成宽度小于硬掩模的较低宽度的有源通道图案。源极/漏极层形成在有源沟道图案和表面的暴露侧面上。选择性地蚀刻栅极层以形成隧道。门将包围活动通道模式并填充隧道。还公开了相关的中间结构。

43. 发明授权

US08198704B2 Semiconductor device including a crystal semiconductor layer 有权
标题翻译：包括晶体半导体层的半导体器件
公开(公告)号：US08198704B2
公开(公告)日：2012-06-12
申请号：US12710378
申请日：2010-02-23
申请人： Sung-Min Kim , Eun-Jung Yun
发明人： Sung-Min Kim , Eun-Jung Yun
IPC分类号： H01L29/06 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/02667 , H01L21/02639 , H01L21/2026 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/785
摘要： In one embodiment, a method of fabricating a semiconductor device having a crystalline semiconductor layer includes preparing a semiconductor substrate and forming a preliminary active pattern on the semiconductor substrate. The preliminary active pattern includes a barrier pattern and a non-single crystal semiconductor pattern. A sacrificial non-single crystal semiconductor layer covers the preliminary active pattern and the semiconductor substrate. By crystallizing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern, using the semiconductor substrate as a seed layer, the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern are changed to a sacrificial crystalline semiconductor layer and a crystalline semiconductor pattern, respectively. The crystalline semiconductor pattern and the barrier pattern constitute an active pattern. The sacrificial crystalline semiconductor layer is removed.
摘要翻译：在一个实施例中，制造具有晶体半导体层的半导体器件的方法包括制备半导体衬底并在半导体衬底上形成预活性图案。预活性图案包括阻挡图案和非单晶半导体图案。牺牲非单晶半导体层覆盖预活性图案和半导体衬底。通过使牺牲非单晶半导体层和非单晶半导体图案结晶，使用半导体衬底作为晶种层，将牺牲非单晶半导体层和非单晶半导体图案改变为牺牲晶体半导体层和晶体半导体图案。晶体半导体图案和势垒图案构成活性图案。去除牺牲晶体半导体层。

44. 发明授权

US07723762B2 Schottky barrier FinFET device and fabrication method thereof 有权
标题翻译：肖特基势垒FinFET器件及其制造方法
公开(公告)号：US07723762B2
公开(公告)日：2010-05-25
申请号：US11598374
申请日：2006-11-13
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
IPC分类号： H01L29/76
CPC分类号： H01L29/41791 , H01L29/66795 , H01L29/7839 , H01L29/78618 , H01L29/78684
摘要： A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is provided. A gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls is provided. The Schottky barrier FinFET device includes a source and a drain which are formed on the sidewalls of the upper fin body adjacent to sidewalls of the gate structure and made of a metal material layer formed on an upper surface of the lower fin body positioned at both sides of the upper fin body, and the source and drain form a Schottky barrier to the lower and upper fin bodies.
摘要翻译：提供肖特基势垒FinFET器件及其制造方法。该装置包括设置在基板上的下部翅片体。提供具有从下翅片体的中心向上延伸并彼此面对的第一和第二侧壁的上翅片本体。提供了一种跨越上翅片体并覆盖上翅片体的上表面和第一和第二侧壁的门结构。肖特基势垒FinFET器件包括源极和漏极，其形成在与鳍结构的侧壁相邻的上翅片体的侧壁上，并且由形成在位于两侧的下翅片体的上表面上的金属材料层并且源极和漏极对下鳍体和上鳍体形成肖特基势垒。

45. 发明授权

US07803697B2 Highly integrated semiconductor device and method of fabricating the same 有权
标题翻译：高度集成的半导体器件及其制造方法
公开(公告)号：US07803697B2
公开(公告)日：2010-09-28
申请号：US11600719
申请日：2006-11-17
申请人： Sung-Min Kim , Eun-Jung Yun
发明人： Sung-Min Kim , Eun-Jung Yun
IPC分类号： H01L21/20
CPC分类号： H01L27/24
摘要： A method of fabricating a semiconductor device includes sequentially forming a first pattern and a second pattern on a substrate, the second pattern being a non-single-crystalline semiconductor stacked on the first pattern, wherein a portion of the substrate is exposed adjacent to the first and second patterns, forming a non-single-crystalline semiconductor layer on the substrate, the semiconductor layer contacting the second pattern and the exposed portion of the substrate, and, using the substrate as a seed layer, changing the crystalline state of the semiconductor layer to be single-crystalline and changing the crystalline state of the second pattern to be single-crystalline.
摘要翻译：一种制造半导体器件的方法包括在衬底上顺序地形成第一图案和第二图案，第二图案是堆叠在第一图案上的非单晶半导体，其中衬底的一部分暴露在与第一图案相邻的第一图案和第二图案，在衬底上形成非单晶半导体层，与第二图案接触的半导体层和衬底的暴露部分，并且使用衬底作为种子层，改变半导体层的结晶状态为单晶，并将第二图案的结晶状态改变为单晶。

46. 发明申请

US20100197099A1 SCHOTTKY BARRIER FiNFET DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：肖特基屏障器件及其制造方法
公开(公告)号：US20100197099A1
公开(公告)日：2010-08-05
申请号：US12759290
申请日：2010-04-13
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/41791 , H01L29/66795 , H01L29/7839 , H01L29/78618 , H01L29/78684
摘要： A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is provided. A gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls is provided. The Schottky barrier FinFET device includes a source and a drain which are formed on the sidewalls of the upper fin body adjacent to sidewalls of the gate structure and made of a metal material layer formed on an upper surface of the lower fin body positioned at both sides of the upper fin body, and the source and drain form a Schottky barrier to the lower and upper fin bodies.
摘要翻译：提供肖特基势垒FinFET器件及其制造方法。该装置包括设置在基板上的下部翅片体。提供具有从下翅片体的中心向上延伸并彼此面对的第一和第二侧壁的上翅片本体。提供了一种跨越上翅片体并覆盖上翅片体的上表面和第一和第二侧壁的门结构。肖特基势垒FinFET器件包括源极和漏极，其形成在与鳍结构的侧壁相邻的上翅片体的侧壁上，并且由形成在位于两侧的下翅片体的上表面上的金属材料层并且源极和漏极对下鳍体和上鳍体形成肖特基势垒。

47. 发明申请

US20100148260A1 SEMICONDUCTOR DEVICE INCLUDING A CRYSTAL SEMICONDUCTOR LAYER, ITS FABRICATION AND ITS OPERATION 有权
标题翻译：半导体器件，包括晶体半导体层，其制造及其操作
公开(公告)号：US20100148260A1
公开(公告)日：2010-06-17
申请号：US12710378
申请日：2010-02-23
申请人： Sung-Min Kim , Eun-Jung Yun
发明人： Sung-Min Kim , Eun-Jung Yun
IPC分类号： H01L29/786
CPC分类号： H01L21/02667 , H01L21/02639 , H01L21/2026 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/785
摘要： In one embodiment, a method of fabricating a semiconductor device having a crystalline semiconductor layer includes preparing a semiconductor substrate and forming a preliminary active pattern on the semiconductor substrate. The preliminary active pattern includes a barrier pattern and a non-single crystal semiconductor pattern. A sacrificial non-single crystal semiconductor layer covers the preliminary active pattern and the semiconductor substrate. By crystallizing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern, using the semiconductor substrate as a seed layer, the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern are changed to a sacrificial crystalline semiconductor layer and a crystalline semiconductor pattern, respectively. The crystalline semiconductor pattern and the barrier pattern constitute an active pattern. The sacrificial crystalline semiconductor layer is removed.
摘要翻译：在一个实施例中，制造具有晶体半导体层的半导体器件的方法包括制备半导体衬底并在半导体衬底上形成预活性图案。预活性图案包括阻挡图案和非单晶半导体图案。牺牲非单晶半导体层覆盖预活性图案和半导体衬底。通过使牺牲非单晶半导体层和非单晶半导体图案结晶，使用半导体衬底作为晶种层，将牺牲非单晶半导体层和非单晶半导体图案改变为牺牲晶体半导体层和晶体半导体图案。晶体半导体图案和势垒图案构成活性图案。去除牺牲晶体半导体层。

48. 发明授权

US07662720B2 3-Dimensional flash memory device and method of fabricating the same 有权
标题翻译： 3维闪存器件及其制造方法
公开(公告)号：US07662720B2
公开(公告)日：2010-02-16
申请号：US12111633
申请日：2008-04-29
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
IPC分类号： H01L21/311
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L29/7926
摘要： In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.
摘要翻译：在一个实施例中，3维快闪存储器件包括：在半导体衬底上沿垂直方向延伸的栅极; 围绕门的电荷存储层; 围绕电荷存储层的硅层; 在所述硅层中垂直形成的沟道区; 以及垂直形成在硅层中的沟道区两侧的源/漏区。可以通过以三维方式存储数据来提高集成度; 可以通过在栅极的两侧提供晶体管来执行2位操作。

49. 发明授权

US07382018B2 3-Dimensional flash memory device and method of fabricating the same 有权
标题翻译： 3维闪存器件及其制造方法
公开(公告)号：US07382018B2
公开(公告)日：2008-06-03
申请号：US11349287
申请日：2006-02-06
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L29/7926
摘要： In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.
摘要翻译：在一个实施例中，3维快闪存储器件包括：在半导体衬底上沿垂直方向延伸的栅极; 围绕门的电荷存储层; 围绕电荷存储层的硅层; 在所述硅层中垂直形成的沟道区; 以及垂直形成在硅层中的沟道区两侧的源/漏区。可以通过以三维方式存储数据来提高集成度; 可以通过在栅极的两侧提供晶体管来执行2位操作。

50. 发明申请

US20070111435A1 Schottky barrier finfet device and fabrication method thereof 有权
标题翻译：肖特基势垒鳍片器件及其制造方法
公开(公告)号：US20070111435A1
公开(公告)日：2007-05-17
申请号：US11598374
申请日：2006-11-13
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
IPC分类号： H01L21/336 , H01L29/76 , H01L21/8242 , H01L29/94
CPC分类号： H01L29/41791 , H01L29/66795 , H01L29/7839 , H01L29/78618 , H01L29/78684
摘要： A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is provided. A gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls is provided. The Schottky barrier FinFET device includes a source and a drain which are formed on the sidewalls of the upper fin body adjacent to sidewalls of the gate structure and made of a metal material layer formed on an upper surface of the lower fin body positioned at both sides of the upper fin body, and the source and drain form a Schottky barrier to the lower and upper fin bodies.
摘要翻译：提供肖特基势垒FinFET器件及其制造方法。该装置包括设置在基板上的下部翅片体。提供具有从下翅片体的中心向上延伸并彼此面对的第一和第二侧壁的上翅片本体。提供了一种跨越上翅片体并覆盖上翅片体的上表面和第一和第二侧壁的门结构。肖特基势垒FinFET器件包括源极和漏极，其形成在与鳍结构的侧壁相邻的上翅片体的侧壁上，并且由形成在位于两侧的下翅片体的上表面上的金属材料层并且源极和漏极对下鳍体和上鳍体形成肖特基势垒。

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