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41. 发明申请

US20060279829A1 ELECTRO-ABSORPTION MODULATOR DEVICE AND METHODS FOR FABRICATING THE SAME 失效
标题翻译：电吸收式调制器装置及其制造方法
公开(公告)号：US20060279829A1
公开(公告)日：2006-12-14
申请号：US11151610
申请日：2005-06-13
申请人： Carl Dohrman , Saurabh Gupta , Eugene Fitzgerald
发明人： Carl Dohrman , Saurabh Gupta , Eugene Fitzgerald
IPC分类号： G02F1/03
CPC分类号： B82Y20/00 , G02F1/017 , G02F2001/0157 , G02F2001/01791
摘要： An electro-absorption light intensity modulator device is provided that comprises a first and a second layer disposed relative to the first layer so as to provide a light-absorbing optical confinement region. The first layer comprises a first insulator layer, and the light-absorbing optical confinement region comprises at least one quantum-confined structure. The at least one quantum-confined structure possesses dimensions such, that upon an application of an electric field in the at least one quantum-confined structure, light absorption is at least partially due to a transition of at least one carrier between a valence state and a conduction state of the at least one quantum-confined structure. A method is also provided for fabricating an electro-absorption light intensity modulator device. The method comprises providing a first insulator layer, disposing a light absorption region over the first insulator layer, and disposing a second insulator layer over the light absorption region, wherein light absorption region comprises at least one quantum-confined structure. The at least one quantum-confined structure possesses dimensions such that, upon an application of an electric field in the at least one quantum-confined structure, light absorption is at least partially due to a transition of at least one carrier between a valence state and a conduction state of the at least one quantum-confined structure.
摘要翻译：提供一种电吸收光强度调制装置，其包括相对于第一层设置的第一和第二层，以便提供光吸收光限制区域。第一层包括第一绝缘体层，并且光吸收光限制区域包括至少一个量子限制结构。所述至少一个量子限制结构具有这样的尺寸，即在施加至少一个量子限制结构中的电场时，光吸收至少部分是由于至少一个载体在价态和所述至少一个量子限制结构的导电状态。还提供了一种用于制造电吸收光强度调制器装置的方法。该方法包括提供第一绝缘体层，在第一绝缘体层上设置光吸收区域，以及在光吸收区域上设置第二绝缘体层，其中光吸收区域包括至少一个量子限制结构。所述至少一个量子限制结构具有这样的尺寸，使得在至少一个量子限制结构中施加电场时，光吸收至少部分是由于至少一个载体在价态和所述至少一个量子限制结构的导电状态。

42. 发明申请

US20060197126A1 Methods for forming structures including strained-semiconductor-on-insulator devices 审中-公开
标题翻译：用于形成包括应变绝缘体上半导体器件的结构的方法
公开(公告)号：US20060197126A1
公开(公告)日：2006-09-07
申请号：US11416423
申请日：2006-05-02
申请人： Anthony Lochtefeld , Thomas Langdo , Richard Hammond , Matthew Currie , Glyn Braithwaite , Eugene Fitzgerald
发明人： Anthony Lochtefeld , Thomas Langdo , Richard Hammond , Matthew Currie , Glyn Braithwaite , Eugene Fitzgerald
IPC分类号： H01L21/8234 , H01L29/76 , H01L31/00
CPC分类号： H01L29/785 , H01L21/76254 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/66795 , H01L29/66916 , H01L29/7842 , H01L29/78603 , H01L29/78684 , H01L29/78687
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
摘要翻译：应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

43. 发明申请

US20060113542A1 Method for forming low defect density alloy graded layers and structure containing such layers 有权
标题翻译：用于形成低缺陷密度合金梯度层的方法和包含这种层的结构
公开(公告)号：US20060113542A1
公开(公告)日：2006-06-01
申请号：US10999486
申请日：2004-11-30
申请人： David Isaacson , Eugene Fitzgerald
发明人： David Isaacson , Eugene Fitzgerald
IPC分类号： H01L29/12 , H01L21/20
CPC分类号： H01L21/02439 , H01L21/0237 , H01L21/02433 , H01L21/0245 , H01L21/02502 , H01L21/0251 , H01L21/02521 , Y10S438/933 , Y10S438/938
摘要： A structure and method of forming same, comprising a low threading density alloy graded layer, deposited according to a deposition temperature profile in correspondence with increasing alloy composition. In one embodiment, a first substantially relaxed alloy graded layer is deposited while varying a deposition temperature according to a first temperature profile. A second substantially relaxed alloy graded layer is deposited over the first graded layer while varying a deposition temperature according to a second temperature profile. Preferably, the minimum signed rate of change of the second temperature profile is less than the maximum signed rate of change of the first temperature profile.
摘要翻译：根据增加的合金成分，根据沉积温度分布沉积低密度合金渐变层的结构和方法。在一个实施例中，在根据第一温度曲线改变沉积温度的同时沉积第一基本上松弛的合金梯度层。第二基本上松弛的合金梯度层沉积在第一梯度层上，同时根据第二温度曲线改变沉积温度。优选地，第二温度分布的最小有效变化率小于第一温度分布的最大有效变化率。

44. 发明申请

US20050280081A1 Semiconductor devices having bonded interfaces and methods for making the same 审中-公开
标题翻译：具有键合界面的半导体器件及其制造方法
公开(公告)号：US20050280081A1
公开(公告)日：2005-12-22
申请号：US10956485
申请日：2004-10-01
申请人： David Isaacson , Gianni Taraschi , Eugene Fitzgerald
发明人： David Isaacson , Gianni Taraschi , Eugene Fitzgerald
IPC分类号： H01L21/3205 , H01L21/8238 , H01L29/06 , H01L29/10 , H01L29/49 , H01L31/0336
CPC分类号： H01L29/1054 , C30B25/18 , H01L21/187 , H01L21/823807 , H01L29/4916 , H01L29/4925 , H01L29/495 , H01L29/4966 , H01L29/78
摘要： A semiconductor-based structure includes first, second, and intermediate layers, with the intermediate layer bonded directly to the first layer, and in contact with the second layer. Parallel to the bonded interface, the lattice spacing of the second layer is different than the lattice spacing of the first layer, though first and second layers are each formed of essentially the same semiconductor. A method for making a semiconductor-based structure includes directly bonding a first layer to an intermediate layer, and providing a second layer in contact with the intermediate layer.
摘要翻译：基于半导体的结构包括第一，第二和中间层，中间层直接结合到第一层，并与第二层接触。平行于键合界面，第二层的晶格间距与第一层的晶格间隔不同，尽管第一和第二层各自由基本上相同的半导体形成。制造基于半导体的结构的方法包括将第一层直接结合到中间层，以及提供与中间层接触的第二层。

45. 发明申请

US20050279992A1 Strained tri-channel layer for semiconductor-based electronic devices 有权
标题翻译：用于基于半导体的电子器件的应变三沟道层
公开(公告)号：US20050279992A1
公开(公告)日：2005-12-22
申请号：US10869463
申请日：2004-06-16
申请人： Saurabh Gupta , Minjoo Lee , Eugene Fitzgerald
发明人： Saurabh Gupta , Minjoo Lee , Eugene Fitzgerald
IPC分类号： H01L21/3205 , H01L21/8238 , H01L29/06 , H01L29/10 , H01L29/49 , H01L31/0336
CPC分类号： H01L21/823807 , H01L29/1054 , H01L29/4916 , H01L29/4925 , H01L29/495 , H01L29/4966
摘要： A semiconductor-based structure includes a substrate layer, a compressively strained semiconductor layer adjacent to the substrate layer to provide a channel for a component, and a tensilely strained semiconductor layer disposed between the substrate layer and the compressively strained semiconductor layer. A method for making an electronic device includes providing, on a strain-inducing substrate, a first tensilely strained layer, forming a compressively strained layer on the first tensilely strained layer, and forming a second tensilely strained layer on the compressively strained layer. The first and second tensilely strained layers can be formed of silicon, and the compressively strained layer can be formed of silicon and germanium.
摘要翻译：基于半导体的结构包括衬底层，与衬底层相邻的压缩应变半导体层以提供用于部件的沟道，以及布置在衬底层和压缩应变半导体层之间的拉伸应变半导体层。一种制造电子器件的方法包括在应变诱导基片上提供第一拉伸应变层，在第一拉伸应变层上形成压缩应变层，以及在压缩应变层上形成第二拉伸应变层。第一和第二拉伸应变层可以由硅形成，并且压缩应变层可以由硅和锗形成。

46. 发明申请

US20050221550A1 Dual layer semiconductor devices 有权
标题翻译：双层半导体器件
公开(公告)号：US20050221550A1
公开(公告)日：2005-10-06
申请号：US11130575
申请日：2005-05-17
申请人： Eugene Fitzgerald
发明人： Eugene Fitzgerald
IPC分类号： H01L21/8238 , H01L29/10
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/1054 , Y10S438/933
摘要： A semiconductor-based device includes a channel layer, which includes a distal layer and a proximal layer in contact with the distal layer. The distal layer supports at least a portion of hole conduction for at least one p-channel component, and the proximal layer supports at least a portion of electron conduction for at least one n-channel component. The proximal layer has a thickness that permits a hole wave function to effectively extend from the proximal layer into the distal layer to facilitate hole conduction by the distal layer. A method for fabricating a semiconductor-based device includes providing a distal portion of a channel layer and providing a proximal portion of the channel layer.
摘要翻译：基于半导体的器件包括沟道层，其包括远端层和与远端层接触的近端层。远端层支撑至少一个p沟道分量的至少一部分空穴传导，并且近端支撑至少一个n沟道分量的至少一部分电子传导。近端层具有允许空穴波函数从近端层有效地延伸到远侧层中的厚度，以便于远端层的空穴传导。一种用于制造基于半导体的器件的方法包括提供沟道层的远端部分并提供沟道层的近端部分。

47. 发明申请

US20050218453A1 Strained-semiconductor-on-insulator device structures with elevated source/drain regions 有权
标题翻译：具有升高的源极/漏极区域的应变半导体绝缘体上器件结构
公开(公告)号：US20050218453A1
公开(公告)日：2005-10-06
申请号：US11125507
申请日：2005-05-10
申请人： Thomas Langdo , Matthew Currie , Richard Hammond , Anthony Lochtefeld , Eugene Fitzgerald
发明人： Thomas Langdo , Matthew Currie , Richard Hammond , Anthony Lochtefeld , Eugene Fitzgerald
IPC分类号： H01L21/20 , H01L21/331 , H01L21/336 , H01L21/337 , H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L29/7847 , H01L21/28518 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1033 , H01L29/165 , H01L29/41783 , H01L29/66242 , H01L29/66628 , H01L29/66772 , H01L29/66787 , H01L29/66916 , H01L29/7842 , H01L29/7843 , H01L29/7849 , H01L29/785 , H01L29/78603 , H01L29/78684 , H01L29/78687
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
摘要翻译：应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

48. 发明申请

US20050189563A1 Strained-semiconductor-on-insulator device structures 有权
标题翻译：应变半导体绝缘体上器件结构
公开(公告)号：US20050189563A1
公开(公告)日：2005-09-01
申请号：US11120675
申请日：2005-05-03
申请人： Anthony Lochtefeld , Thomas Langdo , Richard Hammond , Matthew Currie , Eugene Fitzgerald
发明人： Anthony Lochtefeld , Thomas Langdo , Richard Hammond , Matthew Currie , Eugene Fitzgerald
IPC分类号： H01L21/20 , H01L21/331 , H01L21/336 , H01L21/337 , H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L31/072
CPC分类号： H01L29/7847 , H01L21/28518 , H01L21/76254 , H01L21/76256 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1033 , H01L29/165 , H01L29/41783 , H01L29/66242 , H01L29/66628 , H01L29/66772 , H01L29/66787 , H01L29/66916 , H01L29/7842 , H01L29/7843 , H01L29/7849 , H01L29/785 , H01L29/78603 , H01L29/78684 , H01L29/78687
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
摘要翻译：应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

49. 发明申请

US20050156246A1 METHODS OF FORMING STRAINED-SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES 有权
标题翻译：形成应变半导体绝缘体器件结构的方法
公开(公告)号：US20050156246A1
公开(公告)日：2005-07-21
申请号：US11073780
申请日：2005-03-07
申请人： Anthony Lochtefeld , Thomas Langdo , Richard Hammond , Matthew Currie , Eugene Fitzgerald
发明人： Anthony Lochtefeld , Thomas Langdo , Richard Hammond , Matthew Currie , Eugene Fitzgerald
IPC分类号： H01L21/20 , H01L21/336 , H01L21/337 , H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L31/0392
CPC分类号： H01L21/76254 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02505 , H01L21/0251 , H01L21/02521 , H01L21/02532 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/66916 , H01L29/7842 , H01L29/78603 , H01L29/78684 , H01L29/78687
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
摘要翻译：应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

50. 发明申请

US20050054168A1 Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same 有权
标题翻译：使用具有限定杂质梯度的应变材料层的半导体结构及其制造方法
公开(公告)号：US20050054168A1
公开(公告)日：2005-03-10
申请号：US10972578
申请日：2004-10-25
申请人： Matthew Currie , Anthony Lochtefeld , Richard Hammond , Eugene Fitzgerald
发明人： Matthew Currie , Anthony Lochtefeld , Richard Hammond , Eugene Fitzgerald
IPC分类号： H01L21/20 , H01L21/02 , H01L21/338 , H01L27/12 , H01L29/10 , H01L29/36 , H01L29/778 , H01L29/78 , H01L29/786 , H01L29/812 , H01L21/336
CPC分类号： H01L29/1054 , H01L29/105 , H01L29/161 , H01L29/36 , H01L29/66477 , H01L29/66545 , H01L29/66651 , H01L29/78 , H01L29/7842 , Y10S438/926
摘要： Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
摘要翻译：包括具有无杂质区域的应变材料层的半导体结构和器件及其制造方法。应变材料层的某些区域保持没有可以从半导体的相邻部分相互扩散的杂质。当杂质存在于应变材料层的某些区域中时，器件性能下降。通过采用具有所描述或者根据所描述的步骤制造的特征的半导体结构和器件（例如，场效应晶体管或“FET”），器件操作被增强。

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