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41. 发明授权

US07180648B2 Electro-absorption modulator device and methods for fabricating the same 失效
标题翻译：电吸收式调制装置及其制造方法
公开(公告)号：US07180648B2
公开(公告)日：2007-02-20
申请号：US11151610
申请日：2005-06-13
申请人： Carl Dohrman , Saurabh Gupta , Eugene A. Fitzgerald
发明人： Carl Dohrman , Saurabh Gupta , Eugene A. Fitzgerald
IPC分类号： G02F1/03 , G02F1/01 , H01L31/0328 , H01L31/12 , H01S5/00
CPC分类号： B82Y20/00 , G02F1/017 , G02F2001/0157 , G02F2001/01791
摘要： An electro-absorption light intensity modulator device is provided that comprises a first and a second layer disposed relative to the first layer so as to provide a light-absorbing optical confinement region. The first layer comprises a first insulator layer, and the light-absorbing optical confinement region comprises at least one quantum-confined structure. The at least one quantum-confined structure possesses dimensions such, that upon an application of an electric field in the at least one quantum-confined structure, light absorption is at least partially due to a transition of at least one carrier between a valence state and a conduction state of the at least one quantum-confined structure. A method is also provided for fabricating an electro-absorption light intensity modulator device. The method comprises providing a first insulator layer, disposing a light absorption region over the first insulator layer, and disposing a second insulator layer over the light absorption region, wherein light absorption region comprises at least one quantum-confined structure. The at least one quantum-confined structure possesses dimensions such that, upon an application of an electric field in the at least one quantum-confined structure, light absorption is at least partially due to a transition of at least one carrier between a valence state and a conduction state of the at least one quantum-confined structure.
摘要翻译：提供一种电吸收光强度调制装置，其包括相对于第一层设置的第一和第二层，以便提供光吸收光限制区域。第一层包括第一绝缘体层，并且光吸收光限制区域包括至少一个量子限制结构。所述至少一个量子限制结构具有这样的尺寸，即在施加至少一个量子限制结构中的电场时，光吸收至少部分是由于至少一个载流子在价态和所述至少一个量子限制结构的导电状态。还提供了一种用于制造电吸收光强度调制器装置的方法。该方法包括提供第一绝缘体层，在第一绝缘体层上设置光吸收区域，以及在光吸收区域上设置第二绝缘体层，其中光吸收区域包括至少一个量子限制结构。所述至少一个量子限制结构具有这样的尺寸，使得在至少一个量子限制结构中施加电场时，光吸收至少部分是由于至少一个载体在价态和所述至少一个量子限制结构的导电状态。

42. 发明授权

US07141820B2 Structures with planar strained layers 失效
标题翻译：具有平面应变层的结构
公开(公告)号：US07141820B2
公开(公告)日：2006-11-28
申请号：US10788741
申请日：2004-02-27
申请人： Minjoo L. Lee , Christopher W. Leitz , Eugene A. Fitzgerald
发明人： Minjoo L. Lee , Christopher W. Leitz , Eugene A. Fitzgerald
IPC分类号： H01L29/04
CPC分类号： H01L29/1054 , H01L21/823807 , H01L27/092 , H01L29/78 , H01L29/802
摘要： A structure including a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or equal to 0.25%. A tensilely strained semiconductor layer may be formed over the compressively strained layer. The compressively strained layer is substantially planar, having a surface roughness characterized in (i) having an average wavelength greater than an average wavelength of a carrier in the compressively strained layer and/or (ii) having an average height less than 10 nm.
摘要翻译：包括压缩应变半导体层的结构，该压缩应变层具有大于或等于0.25％的应变。可以在压缩应变层上形成拉伸应变半导体层。压缩应变层基本上是平面的，具有表面粗糙度，其特征在于（i）平均波长大于压缩应变层中的载体的平均波长，和/或（ii）平均高度小于10nm。

43. 发明授权

US06969875B2 Buried channel strained silicon FET using a supply layer created through ion implantation 有权
标题翻译：埋入通道应变硅FET使用通过离子注入产生的供应层
公开(公告)号：US06969875B2
公开(公告)日：2005-11-29
申请号：US09859139
申请日：2001-05-16
申请人： Eugene A. Fitzgerald
发明人： Eugene A. Fitzgerald
IPC分类号： H01L21/335 , H01L21/762 , H01L21/8234 , H01L27/088 , H01L29/10 , H01L29/778 , H01L29/78 , H01L29/786 , H01L31/0328
CPC分类号： H01L29/66431 , H01L21/7624 , H01L21/823412 , H01L27/0883 , H01L29/1054 , H01L29/7782 , H01L29/7838 , H01L29/78687 , Y10S438/933
摘要： A buried channel FET including a substrate, a relaxed SiGe layer, a channel layer, a SiGe cap layer, and an ion implanted dopant supply. The ion implanted dopant supply can be in either the SiGe cap layer or the relaxed SiGe layer. In one embodiment the FET is a MOSFET. In another embodiment the FET is within an integrated circuit. In yet another embodiment, the FET is interconnected to a surface channel FET.
摘要翻译：包括衬底，弛豫SiGe层，沟道层，SiGe覆盖层和离子注入掺杂剂源的掩埋沟道FET。离子注入的掺杂剂供应可以在SiGe覆盖层或松弛的SiGe层中。在一个实施例中，FET是MOSFET。在另一个实施例中，FET在集成电路内。在又一实施例中，FET与表面沟道FET互连。

44. 发明授权

US06846715B2 Gate technology for strained surface channel and strained buried channel MOSFET devices 有权
标题翻译：用于应变表面通道和应变埋入通道MOSFET器件的栅极技术
公开(公告)号：US06846715B2
公开(公告)日：2005-01-25
申请号：US10421154
申请日：2003-04-23
申请人： Eugene A. Fitzgerald , Richard Hammond , Matthew Currie
发明人： Eugene A. Fitzgerald , Richard Hammond , Matthew Currie
IPC分类号： H01L21/20 , H01L21/28 , H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66477 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L21/02664 , H01L21/28194 , H01L21/28211 , H01L21/28238 , H01L29/1054 , H01L29/78 , H01L29/7838 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1−xGex layer on a substrate, a strained channel layer on the relaxed Si1−xGex layer, and a Si1−yGey layer; removing the Si1−yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.
摘要翻译：一种制造半导体器件的方法，包括提供半导体异质结构，在衬底上具有松弛的Si1-xGex层的异质结构，在弛豫的Si1-xGex层上的应变通道层和Si1-yGey层; 去除Si1-yGey层; 并提供介电层。电介质层包括MISFET的栅极电介质。在替代实施例中，异质结构包括SiGe间隔层和Si层。

45. 发明授权

US06830976B2 Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits 有权
标题翻译：轻松的硅锗平台，用于高速CMOS电子和高速模拟电路
公开(公告)号：US06830976B2
公开(公告)日：2004-12-14
申请号：US09906534
申请日：2001-07-16
申请人： Eugene A. Fitzgerald
发明人： Eugene A. Fitzgerald
IPC分类号： H01L21336
CPC分类号： H01L29/802 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/76251 , H01L21/76256 , H01L21/823412 , H01L21/823807 , H01L27/092 , H01L29/1054 , H01L29/165 , H01L29/66431 , H01L29/665 , H01L29/6659 , H01L29/66893 , H01L29/66916 , H01L29/78 , H01L29/7838
摘要： Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
摘要翻译：使用平面弛豫SiGe作为材料平台制造高速数字，模拟和组合数字/模拟系统的结构和方法。松弛的SiGe允许具有增强的电子特性的大量应变Si层。通过允许MOSFET通道处于表面或掩埋，可以创建高速数字和/或模拟电路。在沉积器件外延层之前的平坦化确保了用于最先进光刻的平坦表面。

46. 发明授权

US06677192B1 Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits 有权
标题翻译：制造具有用于高速CMOS电子器件和高速模拟电路的平面化的松弛硅锗平台的方法
公开(公告)号：US06677192B1
公开(公告)日：2004-01-13
申请号：US09906545
申请日：2001-07-16
申请人： Eugene A. Fitzgerald
发明人： Eugene A. Fitzgerald
IPC分类号： H01L2184
CPC分类号： H01L29/802 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/76251 , H01L21/76256 , H01L21/823412 , H01L21/823807 , H01L27/092 , H01L29/1054 , H01L29/66893 , H01L29/66916 , H01L29/7838
摘要： Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography. In accordance with one embodiment of the invention, there is provided a method of fabricating a semiconductor structure including providing a relaxed Si1−xGex layer on a substrate; planarizing said relaxed Si1−xGex layer; and depositing a device heterostructure on said planarized relaxed Si1−xGex layer including at least one strained layer.
摘要翻译：使用平面弛豫SiGe作为材料平台制造高速数字，模拟和组合数字/模拟系统的结构和方法。松弛的SiGe允许具有增强的电子特性的大量应变Si层。通过允许MOSFET通道处于表面或掩埋，可以创建高速数字和/或模拟电路。在沉积器件外延层之前的平坦化确保了用于最先进光刻的平坦表面。根据本发明的一个实施例，提供一种制造半导体结构的方法，包括在衬底上提供松弛的Si1-xGex层; 平坦化所述松弛的Si1-xGex层; 以及在包括至少一个应变层的所述平坦化弛豫Si1-xGex层上沉积器件异质结构。

47. 发明授权

US06555839B2 Buried channel strained silicon FET using a supply layer created through ion implantation 有权
公开(公告)号：US06555839B2
公开(公告)日：2003-04-29
申请号：US09859138
申请日：2001-05-16
申请人： Eugene A. Fitzgerald
发明人： Eugene A. Fitzgerald
IPC分类号： H01L2906
CPC分类号： H01L29/66431 , H01L21/7624 , H01L21/823412 , H01L27/0883 , H01L29/1054 , H01L29/7782 , H01L29/7838 , H01L29/78687 , Y10S438/933
摘要： A circuit including at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET. The depletion mode FET includes an ion implanted dopant supply. In exemplary embodiments, the FETs are surface channel or buried channel MOSFETS. In another exemplary embodiment, the FETs are interconnected to form an inverter.

48. 发明授权

US06521041B2 Etch stop layer system 有权
标题翻译：蚀刻停止层系统
公开(公告)号：US06521041B2
公开(公告)日：2003-02-18
申请号：US09289514
申请日：1999-04-09
申请人： Kenneth C. Wu , Eugene A. Fitzgerald , Jeffrey T. Borenstein
发明人： Kenneth C. Wu , Eugene A. Fitzgerald , Jeffrey T. Borenstein
IPC分类号： C30B2502
CPC分类号： H01L21/02505 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/2007 , H01L21/30608 , H01L21/76256 , Y10S117/915
摘要： A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si1−xGex alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. For example, a cantilever can be made of this etch-stop material system, then released from its substrate and surrounding material, i.e., “micromachined”, by exposure to one of these etchants. These solutions generally etch any silicon containing less than 7×1019 cm−3 of boron or undoped Si1−xGex alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e., differences in etch rate versus pure undoped silicon. This is attributed to the change in energy band structure by the addition of germanium. Furthermore, the nondegenerate doping in the Si1−xGex alloy should not affect the etch-stop behavior. The etch-stop of the invention includes the use of a graded-composition buffer between the silicon substrate and the SiGe etch-stop material. Nominally, the buffer has a linearly-changing composition with respect to thickness, from pure silicon at the substrate/buffer interface to a composition of germanium, and dopant if also present, at the buffer/etch-stop interface which can still be etched at an appreciable rate. Here, there is a strategic jump in germanium and concentration from the buffer side of the interface to the etch-stop material, such that the etch-stop layer is considerably more resistant to the etchant.
摘要翻译：单晶硅衬底上的SiGe单晶蚀刻停止材料体系。蚀刻停止材料系统可以精确的组成变化，但是掺杂或未掺杂的Si1-xGex合金，其x通常在0.2和0.5之间。在其厚度上，蚀刻停止材料本身在组成上是均匀的。蚀刻终止剂用于由诸如氢氧化钾，氢氧化钠，氢氧化锂，乙二胺/邻苯二酚/吡嗪（EDP），TMAH和肼的水的各向异性蚀刻剂的微加工。例如，悬臂可以由该蚀刻停止材料体系制成，然后通过暴露于这些蚀刻剂之一从其衬底和周围的材料即“微加工”释放。这些溶液通常蚀刻含有小于7×10 19 cm -3的小于7×10 19 cm -3的x或x x小于约18的未掺杂的Si1-xGex合金的硅。使用适度浓度的锗合金化硅导致优异的蚀刻选择性，即蚀刻速率与纯未掺杂的差异硅。这归因于通过添加锗的能带结构的变化。此外，Si1-xGex合金中的非退化掺杂不应影响蚀刻停止性能。本发明的蚀刻停止包括在硅衬底和SiGe蚀刻停止材料之间使用渐变组成缓冲液。名义上，缓冲液具有相对于厚度的线性变化的组成，从衬底/缓冲液界面处的纯硅到锗的组成，以及如果还存在，则在缓冲/蚀刻 - 停止界面处的掺杂剂，其仍然可以在一个明显的利率。在这里，从界面的缓冲侧到蚀刻停止材料的锗和浓度存在着战略上的跳跃，使得蚀刻停止层相对于蚀刻剂更具有抵抗力。

49. 发明授权

US06518644B2 Low threading dislocation density relaxed mismatched epilayers without high temperature growth 有权
公开(公告)号：US06518644B2
公开(公告)日：2003-02-11
申请号：US09761508
申请日：2001-01-16
申请人： Eugene A. Fitzgerald
发明人： Eugene A. Fitzgerald
IPC分类号： H01L31117
CPC分类号： C30B25/02 , C30B29/40 , C30B29/42 , C30B29/52 , H01L21/02381 , H01L21/02392 , H01L21/02395 , H01L21/0245 , H01L21/02461 , H01L21/02463 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L21/02543 , H01L21/02546 , H01L21/0262
摘要： A semiconductor structure and method of processing same including a substrate, a lattice-mismatched first layer deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, and a second layer deposited on the first layer with a greater lattice mismatch to the substrate than the first semiconductor layer. In another embodiment there is provided a semiconductor graded composition layer structure on a semiconductor substrate and a method of processing same including a semiconductor substrate, a first semiconductor layer having a series of lattice-mismatched semiconductor layers deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, a second semiconductor layer deposited on the first semiconductor layer with a greater lattice mismatch to the substrate than the first semiconductor layer, and annealed at a temperature greater than 100° C. above the deposition temperature of the second semiconductor layer.

50. 发明授权

US6107653A Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization 失效
标题翻译：使用梯度GeSi层和平面化控制Si中Ge中的穿透位错密度
公开(公告)号：US6107653A
公开(公告)日：2000-08-22
申请号：US103672
申请日：1998-06-23
申请人： Eugene A. Fitzgerald
发明人： Eugene A. Fitzgerald
IPC分类号： H01L21/20 , H01L31/0256
CPC分类号： H01L21/02505 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02502 , H01L21/0251 , H01L21/02532 , Y10S438/933
摘要： A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer oil the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer. In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure including providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer.
摘要翻译：一种半导体结构，包括半导体衬底，在衬底上的至少一个第一晶体外延层，所述第一层具有被平坦化的表面，并且至少一个第二晶体外延层对所述至少一个第一层进行油化。在本发明的另一个实施例中，提供了包括硅衬底和在硅衬底上生长的GeSi分级区域的半导体结构，压缩应变被并入渐变区域以抵消在热处理期间结合的拉伸应变。在本发明的另一个实施例中，提供了一种半导体结构，其包括半导体衬底，具有在衬底上生长的渐变区域的第一层，压缩应变结合在渐变区域中以抵消在热处理期间结合的拉伸应变，所述第一层具有平坦化的表面，以及设置在所述第一层上的第二层。在本发明的另一个实施例中，提供了一种制造半导体结构的方法，包括提供半导体衬底，在衬底上提供至少一个第一晶体外延层，并平坦化第一层的表面。

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