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41. 发明授权

US08065504B2 Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor 有权
标题翻译：使用由指令地址索引的片上和片外查找表来控制处理器中的指令执行
公开(公告)号：US08065504B2
公开(公告)日：2011-11-22
申请号：US11004729
申请日：2004-12-02
申请人： John S. Yates, Jr. , David L. Reese , Paul H. Hohensee , Korbin S. Van Dyke , Shalesh Thusoo , Tiruvur R. Ramesh
发明人： John S. Yates, Jr. , David L. Reese , Paul H. Hohensee , Korbin S. Van Dyke , Shalesh Thusoo , Tiruvur R. Ramesh
IPC分类号： G06F9/30
CPC分类号： G06F9/45533
摘要： A microprocessor chip has instruction pipeline circuitry, and instruction classification circuitry that classifies instructions as they are executed into a small number of classes and records a classification code value. An on-chip table has entries corresponding to a range of addresses of a memory and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer. Lookup circuitry is designed to fetch an entry from the on-chip table as part of the basic instruction processing cycle of the microprocessor. A mask has a value set at least in part by a timer. The instruction pipeline circuitry is controlled based on the value of the on-chip table entry corresponding to the address of instructions processed, the current value of the mask, the recorded classification code, and the off-chip table.
摘要翻译：微处理器芯片具有指令流水线电路和指令分类电路，它们将执行的指令分类为少量类并记录分类代码值。片上表具有对应于存储器的一系列地址的条目，并且被设计为保持在计算机的存储器中查看片外表的值的统计评估。查找电路被设计为从微处理器的基本指令处理周期的一部分获取片上表格中的条目。掩码至少部分由定时器设置的值。基于与所处理的指令的地址，掩码的当前值，记录的分类代码和片外表相对应的片上表项的值来控制指令流水线电路。

42. 发明授权

US06789181B1 Safety net paradigm for managing two computer execution modes 有权
标题翻译：用于管理两台计算机执行模式的安全网范例
公开(公告)号：US06789181B1
公开(公告)日：2004-09-07
申请号：US09432753
申请日：1999-11-03
申请人： John S. Yates , David L. Reese , Korbin S. Van Dyke , Paul H. Hohensee
发明人： John S. Yates , David L. Reese , Korbin S. Van Dyke , Paul H. Hohensee
IPC分类号： G06F944
CPC分类号： G06F9/45533
摘要： A method and computer for executing the method. A source program is translated into an object program, in a manner in which the translated object program has a different execution behavior than the source program. The translated object program is executed under a monitor capable of detecting any deviation from fully-correct interpretation before any side-effect of the different execution behavior is irreversibly committed. When the monitor detects the deviation, or when an interrupt occurs during execution of the object program, a state of the program is established corresponding to a state that would have occurred during an execution of the source program, and from which execution can continue. Execution of the source program continues primarily in a hardware emulator designed to execute instructions of an instruction set non-native to the computer.
摘要翻译：一种用于执行该方法的方法和计算机。源程序被翻译成对象程序，其中翻译的对象程序具有与源程序不同的执行行为。在不可执行行为的任何副作用被不可逆转地提交之前，被翻译的对象程序在能够检测到完全正确解释的任何偏离的监视器下执行。当监视器检测到偏差时，或者在执行对象程序期间发生中断时，根据在源程序执行期间发生的状态并且从哪个执行继续可以建立程序的状态。源程序的执行主要在硬件仿真器中进行，该硬件仿真器旨在执行非本机的指令集的指令。

43. 发明授权

US06324635B1 Method and apparatus for address paging emulation 有权
标题翻译：地址寻呼仿真的方法和装置
公开(公告)号：US06324635B1
公开(公告)日：2001-11-27
申请号：US09328332
申请日：1999-06-09
申请人： Korbin S. Van Dyke , Paul W. Campbell
发明人： Korbin S. Van Dyke , Paul W. Campbell
IPC分类号： G06F1210
CPC分类号： G06F12/1027
摘要： A method and apparatus for address paging emulation includes processing that begins by producing an extended logical address in response to a memory access request. The extended logical address includes a logical address and an address extension. The processing then continues by determining whether an entry exists for the memory access request in a translation look aside table. Such a determination is based on the logical address. When an entry does not exists for the memory access request, the process continues by providing the extended logical address to a plurality of exception handlers. The exception handlers interpret the address extension to identify one of the exception handlers to process the extended logical address. The exception handlers include a page exception handler, a non-page exception handler, a native processor exception handler, and a page directory entry exception handler.
摘要翻译：用于地址寻呼仿真的方法和装置包括响应于存储器访问请求产生扩展逻辑地址开始的处理。扩展逻辑地址包括逻辑地址和地址扩展名。然后通过确定在翻译看待表中是否存在用于存储器访问请求的条目来继续处理。这样的确定是基于逻辑地址。当存储器访问请求不存在条目时，该过程通过向多个异常处理程序提供扩展逻辑地址来继续。异常处理程序解释地址扩展以识别处理扩展逻辑地址的异常处理程序之一。异常处理程序包括页面异常处理程序，非页面异常处理程序，本机处理器异常处理程序和页面目录条目异常处理程序。

44. 发明授权

US06321314B1 Method and apparatus for restricting memory access 有权
标题翻译：用于限制存储器访问的方法和装置
公开(公告)号：US06321314B1
公开(公告)日：2001-11-20
申请号：US09328333
申请日：1999-06-09
申请人： Korbin S. Van Dyke
发明人： Korbin S. Van Dyke
IPC分类号： G06F1200
CPC分类号： G06F21/74 , G06F12/145 , G06F21/79 , G06F2221/2105
摘要： A method and apparatus for restricting memory access includes processing that begins by monitoring memory access requests. When one of the memory access requests is requesting access to restricted memory, determining the mode of operation of the processor. Note that the mode of operation of the processor may be a system special operation (i.e., operations internal to the operation of the computing system that are beyond access of computing system users and programmers), non-system special operations, or a valid response to a restricted memory access request. When the mode of operation is non-system special and the memory access is requesting access to restricted memory, the memory access request is modified. The processing then continues by providing a response in accordance with the modified memory access request.
摘要翻译：用于限制存储器访问的方法和装置包括通过监视存储器访问请求而开始的处理。当其中一个存储器访问请求请求访问受限制的存储器时，确定处理器的操作模式。注意，处理器的操作模式可以是系统特殊操作（即，计算系统的操作的内部操作，超出计算系统用户和程序员的访问），非系统特殊操作或对限制内存访问请求。当操作模式是非系统特殊的并且存储器访问请求访问受限内存时，修改存储器访问请求。然后通过根据修改的存储器访问请求提供响应来继续处理。

45. 发明授权

US5442757A Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts 失效
标题翻译：具有分布式管道控制的计算机处理器，允许功能单元在保持精确中断的同时完成操作
公开(公告)号：US5442757A
公开(公告)日：1995-08-15
申请号：US25439
申请日：1993-03-03
申请人： Harold L. McFarland , David R. Stiles , Korbin S. Van Dyke , Shrenik Mehta , John G. Favor , Dale R. Greenley , Robert A. Cargnoni
发明人： Harold L. McFarland , David R. Stiles , Korbin S. Van Dyke , Shrenik Mehta , John G. Favor , Dale R. Greenley , Robert A. Cargnoni
IPC分类号： G06F9/30 , G06F9/308 , G06F9/318 , G06F9/34 , G06F9/355 , G06F9/38 , G06F11/36 , G06F15/78 , G06F15/16
CPC分类号： G06F11/3648 , G06F15/8053 , G06F9/30003 , G06F9/30018 , G06F9/30167 , G06F9/3017 , G06F9/30185 , G06F9/30189 , G06F9/34 , G06F9/3555 , G06F9/38 , G06F9/3804 , G06F9/3812 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3869 , G06F9/3885
摘要： A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.
摘要翻译：流水线控制系统分布在处理器（10）中的功能单元（15,17,20,25）上。解码器逻辑（12）向功能单元发出每个具有关联标签的操作，最多允许n个操作被显示。单元执行操作并将终止信息报告回解码器逻辑，但不能不可逆转地改变机器的状态。基于终止信息，解码器逻辑依次退出正常终止的操作。如果操作异常终止，则解码器逻辑指示单元退出包括并晚于异常终止的操作的那些操作。

46. 发明授权

US4862346A Index for a register file with update of addresses using simultaneously received current, change, test, and reload addresses 失效
标题翻译：使用同时接收的当前，更改，测试和重新加载地址更新地址的寄存器文件的索引
公开(公告)号：US4862346A
公开(公告)日：1989-08-29
申请号：US751304
申请日：1985-07-02
申请人： Lawrence F. Wagner , Korbin S. Van Dyke , Wayne P. Burleson , Robert D. Hemming , John P. Guadagna
发明人： Lawrence F. Wagner , Korbin S. Van Dyke , Wayne P. Burleson , Robert D. Hemming , John P. Guadagna
IPC分类号： G06F1/03
CPC分类号： G06F1/0307
摘要： A digital processor has four components: a controller, a data converter, a data register, and a logarithmic calculator. The processor has an address bus and a data bus for communication therewith. The address bus is connected to the controller. The data bus is connected to the controller and to the data register. Program instructions from the data bus are supplied to the controller and data on the data bus are supplied to the data register. Program instructions supplied to the controller are decoded and internal program instructions are generated by the controller. The controller communicates with the data converter, data register, and the logarithmic calculator via an internal bus through the internal program instructions. Integer data from the data bus are stored in the data register. The data converter receives the integer data, converts it into logarithmic data, and stores it in the data register. The logarithmic calculator receives the logarithmic data from the data register, operates it thereon, and supplies the resultant logarithmic calculation to the data register for storage. The data converter also communicates with the data register, receives the logarithmic data therefrom and reconverts it back into integer data to be ultimately supplied to the data register. The controller controls the operation of the data converter, data register, and the logarithmic calculator through the internal program instructions supplied on the internal bus.
摘要翻译：数字处理器具有四个部件：控制器，数据转换器，数据寄存器和对数计算器。处理器具有地址总线和与其通信的数据总线。地址总线连接到控制器。数据总线连接到控制器和数据寄存器。来自数据总线的程序指令被提供给控制器，数据总线上的数据被提供给数据寄存器。提供给控制器的程序指令被解码，内部程序指令由控制器产生。控制器通过内部总线通过内部程序指令与数据转换器，数据寄存器和对数计算器进行通信。来自数据总线的整数数据存储在数据寄存器中。数据转换器接收整数数据，将其转换为对数数据，并将其存储在数据寄存器中。对数计算器从数据寄存器接收对数数据，对其进行运算，并将所得到的对数运算提供给数据寄存器进行存储。数据转换器还与数据寄存器进行通信，从其接收对数数据，并将其重新转换为最终提供给数据寄存器的整数数据。控制器通过内部总线上提供的内部程序指令控制数据转换器，数据寄存器和对数计算器的操作。

47. 发明授权

US08127121B2 Apparatus for executing programs for a first computer architechture on a computer of a second architechture 有权
标题翻译：用于在第二建筑物的计算机上执行用于第一计算机建筑物的程序的装置
公开(公告)号：US08127121B2
公开(公告)日：2012-02-28
申请号：US11904007
申请日：2007-09-25
申请人： John S. Yates, Jr. , Matthew F. Storch , Sandeep Nijhawan , Dale R. Jurich , Korbin S. Van Dyke
发明人： John S. Yates, Jr. , Matthew F. Storch , Sandeep Nijhawan , Dale R. Jurich , Korbin S. Van Dyke
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/45554 , G06F9/30174 , G06F9/30189 , G06F9/3861
摘要： Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context. Without modifying a pre-existing operating system of the computer, an entry exception is establishing to be raised on each entry to the operating system at a specified entry point or on a specified condition. The entry exception has an associated entry handler programmed to save a context of an interrupted thread and modify the thread context before delivering the modified context to the operating system. A resumption exception is established to be raised on each resumption from the operating system complementary to one of the specified entries. The resumption exception has an associated exit handler programmed to restore the context saved by a corresponding execution of the entry handler. The entry exception, exit exception, entry handler, and exit handler are cooperatively designed to maintain an association between a one of the threads and an extended context of the thread through a context change induced by the operating system, the extended context including resources of the computer associated with the thread beyond those resources whose association with the thread is maintained by the operating system.
摘要翻译：在第二不同架构的计算机上执行以第一计算机的指令集编码的程序。操作系统维护一组并发线程中的每一个与线程上下文的一组计算机资源之间的关联。在不修改计算机的预先存在的操作系统的情况下，将在指定的入口点或指定条件下建立要在操作系统的每个条目上提出的入口异常。条目异常具有相关联的条目处理程序，其被编程为在将修改的上下文传送到操作系统之前，保存中断的线程的上下文并修改线程上下文。在操作系统的每次恢复之后建立恢复异常，补充指定条目之一。恢复异常具有相关联的退出处理程序，其被编程为恢复由相应执行的条目处理程序保存的上下文。入口异常，退出异常，条目处理程序和退出处理程序被协调地设计为通过由操作系统引发的上下文变化来维护线程中的一个线程和线程的扩展上下文之间的关联，扩展的上下文包括与线程相关联的计算机超出与该线程的关联的那些资源由操作系统维护。

48. 发明授权

US08074055B1 Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code 有权
标题翻译：当执行从第一架构代码流向第二架构代码时，更改处理器的数据存储约定
公开(公告)号：US08074055B1
公开(公告)日：2011-12-06
申请号：US09385394
申请日：1999-08-30
申请人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke , Tiruvur R. Ramesh , Paul H. Hohensee
发明人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke , Tiruvur R. Ramesh , Paul H. Hohensee
IPC分类号： G06F9/30
CPC分类号： G06F9/3005 , G06F9/30174 , G06F9/3804
摘要： A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.
摘要翻译：一台电脑。处理器流水线交替执行针对第一和第二不同计算机体系结构编码的编码或编码以执行第一和第二不同处理惯例的指令。存储器存储由处理器流水线执行的指令，存储器被划分为页面以供虚拟存储器管理器管理，存储器的单个地址空间具有第一和第二页面。存储器单元从存储器中取出指令以由流水线执行，并且获取存储的指示符元素，其与要获取指令的单个地址空间的相应存储器页相关联。每个指示符元素被设计为存储两个不同的计算机体系结构和/或执行约定中的哪一个的指示，在该约定下，相关联的页面的指令数据将由处理器管线执行。存储器单元和/或处理器流水线将来自第一页面的执行流程（其相关联的指示符元素指示第一架构或执行约定）识别到第二页面，其第二页面的相关联的指示符元素指示第一个架构或执行约定。响应于识别，处理器流水线的处理模式或存储器的存储内容适应于执行由该指令页面所对应的指标元素所指示的体系结构和/或规定的指令。

49. 发明授权

US07941647B2 Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination 有权
标题翻译：用于执行两个指令集的计算机，并添加一个宏指令结束标记，用于在循环终止后执行迭代
公开(公告)号：US07941647B2
公开(公告)日：2011-05-10
申请号：US11982419
申请日：2007-10-31
申请人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke , T. R. Ramesh , Paul H. Hohensee
发明人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke , T. R. Ramesh , Paul H. Hohensee
IPC分类号： G06F9/22
CPC分类号： G06F9/30189 , G06F9/30174 , G06F9/30196 , G06F9/3802
摘要： A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.
摘要翻译：一台电脑。处理器流水线交替执行针对第一和第二不同计算机体系结构编码的编码或编码以执行第一和第二不同处理惯例的指令。存储器存储由处理器流水线执行的指令，存储器被划分为页面以供虚拟存储器管理器管理，存储器的单个地址空间具有第一和第二页面。存储器单元从存储器中取出指令以由流水线执行，并且获取存储的指示符元素，其与要获取指令的单个地址空间的相应存储器页相关联。每个指示符元素被设计为存储两个不同的计算机体系结构和/或执行约定中的哪一个的指示，在该约定下，相关联的页面的指令数据将由处理器管线执行。存储器单元和/或处理器流水线将来自第一页面的执行流程（其相关联的指示符元素指示第一架构或执行约定）识别到第二页面，其第二页面的相关联的指示符元素指示第一个架构或执行约定。响应于识别，处理器流水线的处理模式或存储器的存储内容适应于执行由该指令页面所对应的指标元素所指示的体系结构和/或规定的指令。

50. 发明授权

US07254806B1 Detecting reordered side-effects 有权
标题翻译：检测重新排序的副作用
公开(公告)号：US07254806B1
公开(公告)日：2007-08-07
申请号：US09434394
申请日：1999-11-04
申请人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke , Paul H. Hohensee
发明人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke , Paul H. Hohensee
IPC分类号： G06F9/45 , G06F15/00
CPC分类号： G06F9/45558 , G06F9/45554 , G06F2009/45583
摘要： A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effects in the original. The translation distinguishes memory loads that are believed to be directed to well-behaved memory from memory loads that are believed to be directed to non-well-behaved memory device(s). Instruction execution circuitry identifies a memory reference that has a side-effect that has been reordered by translation, the memory reference having been believed at translation time to be directed to well-behaved memory but at execution it is found that the reference cannot be guaranteed to be well-behaved. The instruction execution circuitry identifies whether the difference in side-effect order may have a material effect on the execution of the program. A roll-back program state is established, and execution of the original code resumes.
摘要翻译：计算机二进制翻译器将程序的二进制表示的至少一段从第一指令集架构转换为第二指令集体系结构。翻译中的副作用序列与原始的副作用序列不同。该翻译区分被认为被定向到良好行为的存储器的存储器负载，这些存储器负载相信被定向到不良行为的存储器件。指令执行电路识别具有通过转换重新排序的副作用的存储器引用，已经将翻译时间相信的存储器引用指向良好的存储器，但是在执行时，发现该引用不能被保证表现良好。指令执行电路识别副作用顺序的差异是否可能对程序的执行产生重大影响。建立回滚程序状态，并恢复原始代码的执行。

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