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41. 发明申请

US20050265333A1 Method for enabling efficient multicast transmission in a packet-based network 审中-公开
标题翻译：用于在基于分组的网络中实现有效的多播传输的方法
公开(公告)号：US20050265333A1
公开(公告)日：2005-12-01
申请号：US11047192
申请日：2005-01-31
申请人： John Coffey , Richard Williams
发明人： John Coffey , Richard Williams
IPC分类号： H04L12/18 , H04L12/56 , H04L12/58
CPC分类号： H04L12/1881 , H04L51/38 , H04W4/06 , H04W52/0219 , H04W52/0229 , Y02D70/142 , Y02D70/144 , Y02D70/23
摘要： A communication receiver 52 is disclosed, the receiver operable to receive packets 150, each packet comprising at least a header field 152, a plurality of overhead fields 154, and a plurality of data fields 156, with the overhead fields 154 received contiguous in time to each other and the data fields 156 received contiguous in time to each other and after the overhead fields 154.
摘要翻译：公开了通信接收机52，接收机可操作以接收分组150，每个分组至少包括报头字段152，多个开销字段154和多个数据字段156，其中开销字段154在时间上接收到相邻彼此之间和数据字段156在时间上相互接收并且在开销字段154之后。

42. 发明申请

US20050218427A1 Method for making a FET channel 有权
标题翻译：制造FET通道的方法
公开(公告)号：US20050218427A1
公开(公告)日：2005-10-06
申请号：US11137811
申请日：2005-05-24
申请人： Rajiv Joshi , Richard Williams
发明人： Rajiv Joshi , Richard Williams
IPC分类号： H01L20060101 , H01L21/336 , H01L21/8244 , H01L21/84 , H01L27/01 , H01L27/11 , H01L27/12 , H01L29/06 , H01L29/786 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/785 , H01L21/84 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/42392 , H01L29/66795 , H01L29/78687 , Y10S257/903
摘要： A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78
摘要翻译： FinFET 10的通道16具有沟道芯24和沟道封套32，每个沟道芯32由限定不同晶格结构的半导体材料制成以利用应变硅特性。栅极通过栅极电介质耦合到沟道封套。示例性材料是Si和Si x Ge 1-x x，其中78

43. 发明申请

US20050215013A1 Trench semiconductor device having gate oxide layer with mulitiple thicknesses and processes of fabricating the same 有权
标题翻译：沟槽半导体器件具有多个厚度的栅极氧化物层及其制造方法
公开(公告)号：US20050215013A1
公开(公告)日：2005-09-29
申请号：US11137151
申请日：2005-05-25
申请人： Richard Williams , Wayne Grabowski
发明人： Richard Williams , Wayne Grabowski
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8242 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/4232 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7397 , H01L29/7808 , H01L29/7811 , H01L29/7828 , H01L29/8083
摘要： The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.
摘要翻译：诸如功率MOSFET的沟槽半导体器件通过增加沟槽底部的栅极氧化物层的厚度来减小沟槽拐角处的高电场。描述了用于制造这种设备的几个过程。在一组工艺中，在蚀刻沟槽之后进行氧化硅的定向沉积，在沟槽的底部产生厚的氧化物层。沉积在沟槽壁上的任何氧化物在薄的栅极氧化物层生长在壁上之前被去除。然后在多层或多层中填充沟槽。在该方法的变化中，在蚀刻沟槽的壁之前，在沟槽底部的氧化物上沉积少量的光致抗蚀剂。或者，多晶硅可以沉积在沟槽中并被回蚀，直到只有一部分保留在沟槽的底部。然后将多晶硅氧化，并用多晶硅再填充沟槽。该方法可以组合，随着氧化物的定向沉积，随后是多晶硅的填充和氧化。形成“键孔”形栅电极的工艺包括在沟槽的底部沉积多晶硅，氧化多晶硅的顶表面，蚀刻氧化的多晶硅，并用多晶硅填充沟槽。

44. 发明申请

US20050215012A1 Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same 有权
公开(公告)号：US20050215012A1
公开(公告)日：2005-09-29
申请号：US11137001
申请日：2005-05-25
申请人： Richard Williams , Wayne Grabowski
发明人： Richard Williams , Wayne Grabowski
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8242 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/4232 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7397 , H01L29/7808 , H01L29/7811 , H01L29/7828 , H01L29/8083
摘要： The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

45. 发明申请

US20050142724A1 Method of fabricating isolated semiconductor devices in epi-less substrate 有权
公开(公告)号：US20050142724A1
公开(公告)日：2005-06-30
申请号：US11067212
申请日：2005-02-25
申请人： Richard Williams , Michael Cornell , Wai Chan
发明人： Richard Williams , Michael Cornell , Wai Chan
IPC分类号： H01L21/331 , H01L21/329 , H01L21/761 , H01L21/8222 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L27/08 , H01L27/092 , H01L29/732 , H01L29/861 , H01L23/62
CPC分类号： H01L21/26513 , H01L21/743 , H01L21/761 , H01L21/823878 , H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L29/0878 , H01L29/1083 , H01L29/42368 , H01L29/66136 , H01L29/6625 , H01L29/735 , H01L29/7816 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

46. 发明申请

US20050098286A1 Cut resistant paper and paper articles and method for making same 有权
标题翻译：耐切割纸和纸制品及其制造方法
公开(公告)号：US20050098286A1
公开(公告)日：2005-05-12
申请号：US10967074
申请日：2004-10-15
申请人： Richard Williams , Peter Froass , David Boone , Richard Faber
发明人： Richard Williams , Peter Froass , David Boone , Richard Faber
IPC分类号： D21H19/20 , D21H19/22 , D21H19/28 , D21H21/54 , D21H27/10 , D21H17/33 , D21F11/00
CPC分类号： D21H21/54 , D21H19/20 , D21H19/22 , D21H19/28 , D21H27/10 , Y10T428/1303 , Y10T428/1348 , Y10T428/24215 , Y10T428/26 , Y10T428/277 , Y10T428/2985
摘要： The specification discloses a method for making a paper material having a reduced tendency to cut human skin. The method includes providing a papermaking furnish containing cellulosic fibers and from about 0.5 to about 5.0 wt % by weight dry basis expandable microspheres, forming a paperboard web from the papermaking furnish, drying the web, and calendaring the web to a caliper of from about 11.0 to about 18.0 mils and a density ranging from about 7.0 to about 12.0 lb/3000 ft2/mil. Papers formed according to the method and articles formed therefrom are also disclosed.
摘要翻译：本说明书公开了一种制造具有降低人皮肤倾向的纸材的方法。该方法包括提供含有纤维素纤维的造纸配料和约0.5至约5.0wt％的干基可膨胀微球，从造纸配料形成纸板纤维网，干燥纤维网，并将幅材压延至约11.0的厚度至约18.0密耳，密度范围为约7.0至约12.0lb / 3000ft 2 / mil。还公开了根据该方法形成的纸和由其形成的制品。

47. 发明申请

US20050089913A1 Compositions and methods for the identification and selection of nucleic acids and polypeptides 有权
标题翻译：用于鉴定和选择核酸和多肽的组合物和方法
公开(公告)号：US20050089913A1
公开(公告)日：2005-04-28
申请号：US10960453
申请日：2004-10-07
申请人： Richard Williams
发明人： Richard Williams
IPC分类号： C12N15/10 , A61K48/00 , C07H21/02 , C12Q1/68
CPC分类号： C12N15/1034 , C12N15/1062 , G01N33/58 , G01N33/6845 , G01N2458/10
摘要： This invention relates generally to systems and methods for identifying and selecting, desired proteins or nucleic acid molecules by linking mRNA, with known or unknown sequences, to its translated protein to form a cognate pair. The cognate pair is selected based upon desired properties of the protein or the nucleic acid. This method also includes the evolution of a desired protein or nucleic acid molecule by amplifying the nucleic acid portion of the selected cognate pair, introducing variation into the nucleic acid, translating the nucleic acid, attaching the nucleic acid to its protein to form a second cognate pair, and re-selecting this cognate pair based upon desired properties. Modified mRNAs operable to crosslink to tRNAs are also provided. Methods of producing a psoralen monoadduct or a crosslink are also provided.
摘要翻译：本发明一般涉及通过将mRNA与已知或未知序列连接到其翻译的蛋白质以形成同源对来鉴定和选择所需蛋白质或核酸分子的系统和方法。基于蛋白质或核酸的所需性质选择同源对。该方法还包括通过扩增所选择的同源对的核酸部分，引入核酸的变异，翻译核酸，将核酸连接到其蛋白质以形成第二个同源物，从而演化期望的蛋白质或核酸分子并且基于所需的属性重新选择该同源对。还提供了可操作以交联至tRNA的修饰的mRNA。还提供了补骨脂素单加成物或交联剂的制备方法。

48. 发明授权

US06881351B2 Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices 有权
标题翻译：用于接触覆盖MRAM器件的电磁元件的导电层的方法
公开(公告)号：US06881351B2
公开(公告)日：2005-04-19
申请号：US10421096
申请日：2003-04-22
申请人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Kelly Kyler , Charles A. Synder , Kenneth H. Smith , Clarence J. Tracy , Richard Williams
发明人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Kelly Kyler , Charles A. Synder , Kenneth H. Smith , Clarence J. Tracy , Richard Williams
IPC分类号： G11C11/15 , H01L21/8246 , H01L43/12 , H01L21/00
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/15 , H01L43/12
摘要： A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.
摘要翻译：用于使覆盖磁电元件的导电层接触的方法包括形成覆盖电介质区域的存储元件层。沉积在存储元件层上的第一导电层。第一电介质层沉积在第一导电层上，并被图案化和蚀刻以形成第一掩模层。使用第一掩模层，蚀刻第一导电层。沉积第二介电层，覆盖第一掩模层和电介质区域。去除第二介电层的一部分以露出第一掩模层。对第二介电层和第一掩模层进行蚀刻化学处理，使得以比第二介电层更快的速率蚀刻第一掩模层。蚀刻暴露第一导电层。

49. 发明申请

US20050038421A1 Controllable pressure cryogenic balloon treatment system and method 有权
标题翻译：可控压力低温球囊治疗系统及方法
公开(公告)号：US20050038421A1
公开(公告)日：2005-02-17
申请号：US10455253
申请日：2003-06-04
申请人： James Joye , Richard Williams , Glen Reuschling
发明人： James Joye , Richard Williams , Glen Reuschling
IPC分类号： A61B17/22 , A61B18/02 , A61B18/18 , A61N20060101
CPC分类号： A61B18/02 , A61B2017/22001 , A61B2017/22051 , A61B2018/0022 , A61B2018/0212 , A61B2018/0262
摘要： Devices, systems, and methods controllably cool blood vessels and other body lumens. The blood vessel will often be treated for atherosclerotic or other diseases by inflating a balloon so as to engage the surrounding luminal wall. Controlled cooling of the balloon effected by a change in phase of a cryogenic fluid within the balloon typically a change from a liquid phase to a gas phase can be provided with a controlled, gradual inflation of the balloon. A single control system can be used for any of a variety of alternative selectable balloon catheters having significantly differing cooling fluid flow characteristics.
摘要翻译：装置，系统和方法可控地冷却血管和其他体腔。血管通常通过充气气球来治疗动脉粥样硬化或其它疾病，从而与周围的腔壁接合。通过气囊内的低温流体的相位变化而实现的气囊的受控制冷却通常可以从液相到气相的变化被控制地逐渐膨胀气囊。单个控制系统可以用于具有显着不同的冷却流体流动特性的各种可选择的可选气囊导管中的任何一种。

50. 发明申请

US20050023606A1 Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology 有权
标题翻译：模块化双极CMOS-DMOS模拟集成电路和功率晶体管技术
公开(公告)号：US20050023606A1
公开(公告)日：2005-02-03
申请号：US10767751
申请日：2004-01-28
申请人： Richard Williams , Michael Cornell , Wai Chan
发明人： Richard Williams , Michael Cornell , Wai Chan
IPC分类号： H01L21/762 , H01L21/8228 , H01L21/8234 , H01L21/8238 , H01L29/423 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7816 , H01L21/26513 , H01L21/2652 , H01L21/74 , H01L21/743 , H01L21/76216 , H01L21/76218 , H01L21/82285 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L21/8249 , H01L27/0623 , H01L27/0922 , H01L29/4232 , H01L29/4238 , H01L29/66272 , H01L29/7322 , H01L29/7809 , H01L29/7813 , H01L29/7835
摘要： A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
摘要翻译：在不含外延层的基板中形成半导体器件系列。在一个实施例中，该系列包括5V CMOS对，12V CMOS对，5V NPN，5V PNP，多种形式的横向沟槽MOSFET和30V侧向N沟道DMOS。每个装置在横向和垂直方面非常紧凑，并且可以与基板中的所有其它装置完全隔离。

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