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41. 发明申请

US20090142895A1 METHOD OF FORMING A VIA 有权
标题翻译：形成威盛的方法
公开(公告)号：US20090142895A1
公开(公告)日：2009-06-04
申请号：US11948209
申请日：2007-11-30
申请人： Tab A. Stephens , Olubunmi O. Adetutu , Paul A. Grudowski , Matthew T. Herrick
发明人： Tab A. Stephens , Olubunmi O. Adetutu , Paul A. Grudowski , Matthew T. Herrick
IPC分类号： H01L21/8234
CPC分类号： H01L21/823871 , H01L21/76897 , H01L21/823468 , H01L21/823475 , H01L29/665
摘要： A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.
摘要翻译：形成通孔的方法包括在半导体衬底上形成栅电极，在与栅电极相邻的半导体衬底中形成源极/漏极区域，在源/漏区域中形成硅化物区域，形成邻近硅化物间隔区在形成硅化物区域之后形成栅电极，在栅电极，硅化物间隔物和硅化物区域之上形成层间电介质层，并且在层间电介质层中形成延伸到硅化物区域的导电通孔。

42. 发明申请

US20080248649A1 First inter-layer dielectric stack for non-volatile memory 有权
标题翻译：用于非易失性存储器的第一层间介质叠层
公开(公告)号：US20080248649A1
公开(公告)日：2008-10-09
申请号：US11697106
申请日：2007-04-05
申请人： Olubunmi O. Adetutu , Christopher B. Hundley , Paul A. Ingersoll , Craig T. Swift
发明人： Olubunmi O. Adetutu , Christopher B. Hundley , Paul A. Ingersoll , Craig T. Swift
IPC分类号： H01L21/311
CPC分类号： H01L21/31612 , H01L21/02164 , H01L21/02271 , H01L21/02362 , H01L21/31116 , H01L21/31144 , H01L21/3221 , H01L21/76816 , H01L21/76829 , H01L21/76832 , H01L21/76837 , H01L27/115 , H01L27/11521 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus are described for forming a first inter-layer dielectric (ILD0) stack having a protective gettering layer (72) with a substantially uniform thickness. After forming device components (32, 33) on a substrate (31), a gap fill dielectric layer of SATEOS (52) is deposited over an etch stop layer of PEN ESL (42) and then planarized before sequentially depositing a gettering layer of BPTEOS (72) and capping dielectric layer (82) on the planarized gap fill dielectric layer (52). Once the ILD0 stack is formed, one or more contact openings (92, 94, 96) are etched through the ILD0 stack, thereby exposing the etch stop layer (42) over the intended contact regions.
摘要翻译：描述了一种用于形成具有基本均匀厚度的保护性吸气层（72）的第一层间电介质（ILD0）堆叠的方法和装置。在衬底（31）上形成器件部件（32,33）之后，将SATEOS（52）的间隙填充电介质层沉积在PEN ESL（42）的蚀刻停止层上，然后在顺序沉积BPTEOS吸气层之前进行平坦化（72）和在平坦化间隙填充介电层（52）上的覆盖电介质层（82）。一旦形成了ILD0堆叠，就通过ILD0堆叠蚀刻一个或多个接触开口（92,94,96），从而将蚀刻停止层（42）暴露在预期的接触区域上。

43. 发明授权

US07432164B2 Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same 有权
标题翻译：包括具有反掺杂沟道区的晶体管的半导体器件及其形成方法
公开(公告)号：US07432164B2
公开(公告)日：2008-10-07
申请号：US11342025
申请日：2006-01-27
申请人： Olubunmi O. Adetutu , David C. Gilmer , Philip J. Tobin
发明人： Olubunmi O. Adetutu , David C. Gilmer , Philip J. Tobin
IPC分类号： H01L21/8236 , H01L21/336 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823842
摘要： A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second conductivity type different from the first conductivity type. The method further includes forming a dielectric layer over at least a portion of the first substrate region and at least a portion of the second substrate region. The method further includes forming a metal-containing gate layer over at least a portion of the dielectric layer overlying the first substrate region. The method further includes introducing dopants into at least a portion of the first substrate region through the metal-containing gate layer.
摘要翻译：一种制造半导体器件的方法包括提供第一衬底区域和第二衬底区域，其中第一衬底区域的至少一部分具有第一导电类型，并且第二衬底区域的至少一部分具有不同的第二导电类型从第一导电类型。该方法还包括在第一衬底区域的至少一部分和第二衬底区域的至少一部分上形成电介质层。该方法还包括在覆盖第一衬底区域的介电层的至少一部分上形成含金属的栅极层。该方法还包括通过含金属的栅极层将掺杂剂引入到第一衬底区域的至少一部分中。

44. 发明授权

US07297588B2 Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities and a process for forming the same 有权
标题翻译：电子器件包括含有含有一种或多种杂质的含金属层的栅电极及其形成方法
公开(公告)号：US07297588B2
公开(公告)日：2007-11-20
申请号：US11046079
申请日：2005-01-28
申请人： Olubunmi O. Adetutu , David C. Gilmer , Philip J. Tobin
发明人： Olubunmi O. Adetutu , David C. Gilmer , Philip J. Tobin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842
摘要： One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.
摘要翻译：可以在含金属的栅电极的含金属层内并入一种或多种杂质以改变晶体管的含金属栅电极的功函数可影响晶体管的阈值电压。在一个实施例中，杂质可用于p沟道晶体管，以允许含金属的栅电极的功函数更接近硅的价带。在另一实施例中，杂质可用于n沟道晶体管，以允许含金属的栅电极的功函数更接近于硅的导带。在一个具体的实施方案中，将含硼物质注入到在p沟道晶体管内的含金属栅电极内的含金属层中，使得含金属栅电极具有更接近价带的功函数与没有含硼物质的含金属栅电极相比。

45. 发明授权

US07045432B2 Method for forming a semiconductor device with local semiconductor-on-insulator (SOI) 有权
标题翻译：用局部绝缘体半导体（SOI）形成半导体器件的方法
公开(公告)号：US07045432B2
公开(公告)日：2006-05-16
申请号：US10771855
申请日：2004-02-04
申请人： Marius K. Orlowski , Olubunmi O. Adetutu , Alexander L. Barr
发明人： Marius K. Orlowski , Olubunmi O. Adetutu , Alexander L. Barr
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L29/66772 , H01L29/785 , H01L29/78603
摘要： A semiconductor on insulator transistor is formed beginning with a bulk silicon substrate. An active region is defined in the substrate and an oxygen-rich silicon layer that is monocrystalline is formed on a top surface of the active region. On this oxygen-rich silicon layer is grown an epitaxial layer of silicon. After formation of the epitaxial layer of silicon, the oxygen-rich silicon layer is converted to silicon oxide while at least a portion of the epitaxial layer of silicon remains as monocrystalline silicon. This is achieved by applying high temperature water vapor to the epitaxial layer. The result is a silicon on insulator structure useful for making a transistor in which the gate dielectric is on the remaining monocrystalline silicon, the gate is on the gate dielectric, and the channel is in the remaining monocrystalline silicon under the gate.
摘要翻译：半导体绝缘体晶体管以体硅衬底开始形成。在衬底中限定有源区，并且在有源区的顶表面上形成单晶的富氧硅层。在该富氧硅层上生长硅的外延层。在形成硅的外延层之后，将富氧硅层转化为氧化硅，而硅的外延层的至少一部分保留为单晶硅。这通过将高温水蒸气施加到外延层来实现。结果是用于制造晶体管的绝缘体上硅结构，其中栅极电介质位于剩余的单晶硅上，栅极位于栅极电介质上，沟道位于栅极之下的剩余单晶硅中。

46. 发明授权

US06908852B2 Method of forming an arc layer for a semiconductor device 有权
标题翻译：形成半导体器件的电弧层的方法
公开(公告)号：US06908852B2
公开(公告)日：2005-06-21
申请号：US10353886
申请日：2003-01-29
申请人： Olubunmi O. Adetutu , Donald O. Arugu
发明人： Olubunmi O. Adetutu , Donald O. Arugu
IPC分类号： G03F20060101 , G03F7/09 , H01L21/027 , H01L21/302 , H01L21/4763 , H01L23/48 , H01L23/58
CPC分类号： H01L21/0276 , G03F7/091
摘要： An antireflective coating (ARC) layer for use in the manufacture of a semiconductor device. The ARC layer has a bottom portion that has a lower percentage of silicon than a portion of the ARC layer located above it. The ARC layer is formed on a metal layer, wherein the lower percentage of silicon of the ARC layer inhibits the unwanted formation of suicides at the metal layer/ARC layer interface. In some embodiments, the top portion of the ARC layer has a lower percentage of silicon than the middle portion of the ARC layer, wherein the lower percentage of silicon at the top portion may inhibit the poisoning of a photo resist layer on the ARC layer. In one embodiment, the percentage of silicon can be increased or decreased by decreasing or increasing the ratio of the flow rate of a nitrogen containing gas with respect to the flow rate of a silicon containing gas during a deposition process.
摘要翻译：一种用于制造半导体器件的抗反射涂层（ARC）层。 ARC层具有比位于其上方的ARC层的一部分具有较低百分比的硅的底部。 ARC层形成在金属层上，其中ARC层的较低百分比的硅在金属层/ ARC层界面处抑制不必要的自杀形成。在一些实施例中，ARC层的顶部具有比ARC层的中间部分更低的硅百分比，其中在顶部部分的较低百分比的硅可以抑制ARC层上的光致抗蚀剂层的中毒。在一个实施方案中，通过降低或增加含氮气体的流量相对于沉积过程中的含硅气体的流速的比例，可以增加或减少硅的百分比。

47. 发明授权

US06423619B1 Transistor metal gate structure that minimizes non-planarity effects and method of formation 有权
标题翻译：晶体管金属栅极结构使非平面效应和形成方法最小化
公开(公告)号：US06423619B1
公开(公告)日：2002-07-23
申请号：US09997899
申请日：2001-11-30
申请人： John M. Grant , Olubunmi O. Adetutu , Yolanda S. Musgrove
发明人： John M. Grant , Olubunmi O. Adetutu , Yolanda S. Musgrove
IPC分类号： H01L213205
CPC分类号： H01L29/66583 , H01L21/28088 , H01L29/4966
摘要： A metal gate structure is formed by depositing a gate dielectric, a gate electrode, a stop layer, and a metal layer within a gate trench and removing the portions of the layers that lie outside the gate trench. A first polish or etch process is used to remove a portion of the metal layer selective to the stop layer. A second polish or etch process is used to remove portions of the gate dielectric, the gate electrode, the stop layer and the metal layer which lie outside the gate trench after the first polish or etch process. The resulting structure increases the uniformity and non-planarity of the top surface of the metal gate structure.
摘要翻译：通过在栅极沟槽内沉积栅极电介质，栅极电极，停止层和金属层并去除位于栅极沟槽外部的层的部分来形成金属栅极结构。使用第一抛光或蚀刻工艺去除对停止层有选择性的金属层的一部分。在第一抛光或蚀刻工艺之后，使用第二抛光或蚀刻工艺去除位于栅极沟槽外部的栅极电介质，栅电极，停止层和金属层的部分。所得到的结构增加了金属栅极结构的顶表面的均匀性和非平面性。

48. 发明授权

US08125032B2 Modified hybrid orientation technology 有权
标题翻译：改进的混合取向技术
公开(公告)号：US08125032B2
公开(公告)日：2012-02-28
申请号：US12421247
申请日：2009-04-09
申请人： Olubunmi O. Adetutu , Mariam G. Sadaka , Ted R. White , Bich-Yen Nguyen
发明人： Olubunmi O. Adetutu , Mariam G. Sadaka , Ted R. White , Bich-Yen Nguyen
IPC分类号： H01L21/02
CPC分类号： H01L21/823878 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L27/1207
摘要： A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). By forming the first gate electrode (151) over a first SOI substrate (90) formed by depositing (100) silicon and forming the second gate electrode (161) over an epitaxially grown (110) SiGe substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.
摘要翻译：半导体工艺和装置包括通过在第一高k栅极电介质（121）上形成第一栅极电极（151）并在第二栅极电极（121）上形成第二栅极电极（151）而在混合衬底（17）上形成第一和第二金属栅电极（151,161）电极（161）在与第一栅极电介质（121）不同的至少第二高k栅极电介质（122）之上。通过在通过在外延生长（110）SiGe衬底（70）上沉积（100）硅并形成第二栅电极（161）而形成的第一SOI衬底（90）上形成第一栅电极（151），高性能CMOS 获得包括具有改善的空穴迁移率的高k金属PMOS栅电极（161）的器件。

49. 发明授权

US07981808B2 Method of forming a gate dielectric by in-situ plasma 有权
标题翻译：通过原位等离子体形成栅极电介质的方法
公开(公告)号：US07981808B2
公开(公告)日：2011-07-19
申请号：US12241139
申请日：2008-09-30
申请人： Tien Ying Luo , Olubunmi O. Adetutu
发明人： Tien Ying Luo , Olubunmi O. Adetutu
IPC分类号： H01L21/3205 , H01L21/31 , H01L21/336
CPC分类号： H01L21/31645 , C23C16/40 , C23C16/402 , C23C16/405 , C23C16/452 , C23C16/45536 , H01L21/02164 , H01L21/02181 , H01L21/02274 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L21/31612 , H01L21/31641 , H01L29/517
摘要： A method of forming a gate dielectric layer includes forming a first dielectric layer over a semiconductor substrate using a first plasma, performing a first in-situ plasma nitridation of the first dielectric layer to form a first nitrided dielectric layer, forming a second dielectric layer over the first dielectric layer using a second plasma, performing a second in-situ plasma nitridation of the second dielectric layer to form a second nitrided dielectric layer; and annealing the first nitrided dielectric layer and the second nitrided dielectric layer, wherein the gate dielectric layer comprises the first nitrided dielectric layer and the second nitrided dielectric layer. In other embodiments, the steps of forming a dielectric layer using a plasma and performing an in-situ plasma nitridation are repeated so that more than two nitrided dielectric layers are formed and used as the gate dielectric layer.
摘要翻译：一种形成栅极电介质层的方法包括：使用第一等离子体在半导体衬底上形成第一电介质层，执行第一介电层的第一原位等离子体氮化，形成第一氮化电介质层，形成第二电介质层使用第二等离子体的第一电介质层，执行第二介电层的第二原位等离子体氮化以形成第二氮化介电层; 以及对所述第一氮化介电层和所述第二氮化介电层进行退火，其中所述栅介质层包括所述第一氮化介电层和所述第二氮化介电层。在其他实施例中，重复使用等离子体形成电介质层并执行原位等离子体氮化的步骤，以形成多于两个的氮化电介质层并用作栅极电介质层。

50. 发明授权

US07745298B2 Method of forming a via 有权
标题翻译：形成通孔的方法
公开(公告)号：US07745298B2
公开(公告)日：2010-06-29
申请号：US11948209
申请日：2007-11-30
申请人： Tab A. Stephens , Olubunmi O. Adetutu , Paul A. Grudowski , Matthew T. Herrick
发明人： Tab A. Stephens , Olubunmi O. Adetutu , Paul A. Grudowski , Matthew T. Herrick
IPC分类号： H01L21/336
CPC分类号： H01L21/823871 , H01L21/76897 , H01L21/823468 , H01L21/823475 , H01L29/665
摘要： A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.
摘要翻译：形成通孔的方法包括在半导体衬底上形成栅电极，在与栅电极相邻的半导体衬底中形成源极/漏极区域，在源/漏区域中形成硅化物区域，形成邻近硅化物间隔区在形成硅化物区域之后形成栅电极，在栅电极，硅化物间隔物和硅化物区域之上形成层间电介质层，并且在层间电介质层中形成延伸到硅化物区域的导电通孔。

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