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41. 发明授权

US07260491B2 Duty cycle measurement apparatus and method 失效
公开(公告)号：US07260491B2
公开(公告)日：2007-08-21
申请号：US11260570
申请日：2005-10-27
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F19/00
CPC分类号： G01R29/02 , G01R31/2884
摘要： A mechanism for measuring duty cycle of a signal under test in an integrated circuit device, such as a microprocessor or system-on-a-chip is provided. The mechanism generates a frequency which is proportional to the duty cycle and which can be measured using common lab or manufacturing equipment. The mechanism may be implemented using simple circuits in a standard complementary metal oxide semiconductor process which requires very little area and can be powered off when it is not being used. The mechanism may include, for example, a low pass filter, a voltage divider for providing calibration reference voltage signals, a voltage to frequency converter, a frequency divider for dividing a frequency signal output so that the frequency of the signal is within a predetermined range, and an output driver and output pad. From the frequency output signal, a duty cycle of the signal under test may be calculated using off-chip equipment.

42. 发明授权

US07245172B2 Level shifter apparatus and method for minimizing duty cycle distortion 失效
标题翻译：用于最小化占空比失真的电平移位器装置和方法
公开(公告)号：US07245172B2
公开(公告)日：2007-07-17
申请号：US11269245
申请日：2005-11-08
申请人： David W. Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A level shifter apparatus and method for minimizing duty cycle distortion are provided. The level shifter includes a bank of comparators each having an associated threshold built into it. The comparators compare a difference in source voltages for two power domains to these built-in thresholds and output a signal indicative of whether the threshold is exceeded. The output signals from the comparators are provided to a thermometric decoder which generates control signals based on these output signals. The control signals are used to control stages in a level shifter for modifying the voltage output of the level shifter. Individual stages may be enabled to thereby monotonically modify the voltage output of the level shifter and thereby decrease a time required to achieve a voltage having a level that causes a state change in a driven circuit. As a result, duty cycle distortion is minimized and maximum operational frequency is increased.
摘要翻译：提供了一种用于最小化占空比失真的电平移位器装置和方法。电平移位器包括一组比较器，每个比较器具有内置在其中的相关联的阈值。比较器将两个功率域的源电压差与这些内置阈值进行比较，并输出一个指示阈值是否超过的信号。来自比较器的输出信号被提供给基于这些输出信号产生控制信号的温度测量解码器。控制信号用于控制电平移位器中用于修改电平移位器的电压输出的级。单个级可以被使能，从而单调地修改电平转换器的电压输出，从而减少实现具有使驱动电路中的状态变化的电平的电压所需的时间。结果，占空比失真被最小化并且最大的操作频率增加。

43. 发明授权

US5274285A Enhanced differential current switch compensating upshift circuit 失效
标题翻译：增强差动电流开关补偿升档电路
公开(公告)号：US5274285A
公开(公告)日：1993-12-28
申请号：US940252
申请日：1992-09-01
申请人： David W. Boerstler , Edward B. Eichelberger , Gary T. Hendrickson , Charles B. Winn
发明人： David W. Boerstler , Edward B. Eichelberger , Gary T. Hendrickson , Charles B. Winn
IPC分类号： H03K3/286 , H03K19/092 , H03K19/086
CPC分类号： H03K3/286
摘要： A compensating upshift circuit providing low signal degradation and operating at high speed and at low power. Capacitor shunted diodes cross-couple the collectors and bases of two transistors. The cross-coupling eliminates signal swing degradation in the upshift circuit and controls current through the two collector resistors. Equalized collector resistor current eliminates signal swing degradation while providing an upshift circuit with short delays. The capacitor shunted diodes can be replaced by diode connected transistors configured to provide the necessary collector-base capacitance.
摘要翻译：补偿升档电路提供低信号衰减，并以高速和低功率运行。电容分流二极管交叉耦合两个晶体管的集电极和基极。交叉耦合消除了升档电路中的信号摆幅恶化，并控制通过两个集电极电阻的电流。均衡集电极电流消除了信号摆幅下降，同时提供了具有短延迟的升档电路。电容器分流二极管可以由配置为提供必要的集电极基极电容的二极管连接的晶体管替代。

44. 发明授权

US08381143B2 Structure for a duty cycle correction circuit 失效
标题翻译：占空比校正电路的结构
公开(公告)号：US08381143B2
公开(公告)日：2013-02-19
申请号：US13014828
申请日：2011-01-27
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F17/50
CPC分类号： H03K5/1565 , H03K2005/00058 , H03K2005/00221
摘要： A design structure for a Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.
摘要翻译：提供了一种用于占空比校正（DCC）电路的设计结构，其中已知DCC电路拓扑中的场效应晶体管（FET）中的对被替换为与DCC电路的开关耦合的线性电阻器，使得当开关断开时，输入信号通过线性电阻器路由。线性电阻器比FET更容忍工艺，电压和温度（PVT）波动，因此，所得到的DCC电路与使用FET的已知DCC电路拓扑结构相比，具有PVT波动的DCC校正范围相对较小的变化。线性电阻器可以与开关并联设置并且与具有相对较大电阻值的一对FET串联。线性电阻器提供上拉或下拉输入信号的脉冲宽度的电阻，以便对输入信号的占空比提供校正。

45. 发明授权

US07786813B2 Interleaved voltage controlled oscillator 有权
公开(公告)号：US07786813B2
公开(公告)日：2010-08-31
申请号：US12098490
申请日：2008-04-07
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
IPC分类号： H03K3/03
CPC分类号： H03L7/0995 , H03K3/0315 , H03K5/133
摘要： An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.

46. 发明授权

US07782146B2 Interleaved voltage controlled oscillator 有权
标题翻译：交错压控振荡器
公开(公告)号：US07782146B2
公开(公告)日：2010-08-24
申请号：US12098483
申请日：2008-04-07
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
IPC分类号： H03K3/03
CPC分类号： H03L7/0995 , H03K3/0315 , H03K5/133
摘要： An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.
摘要翻译：公开了一种交错压控振荡器（VCO）。 VCO包括环形电路，其包括主逻辑反相器门的串联连接，与主逻辑反相器门的选定序列并联连接的多个延迟元件，至少一个温度补偿电路，包括与一个或多个场效应晶体管，所述场效应晶体管响应于与温度成比例的补偿电压输入;以及电子电路，其与所述至少一个温度补偿电路进行信号通信，并且被配置为提供响应于温度的电压信号。每个延迟元件包括前馈部分，其包括用于响应于一个或多个控制电压来调节通过前馈元件的信号传输的控制，以及比例部分，包括用于调节通过至少一个逻辑反相器门的信号传输的控制。

47. 发明申请

US20090146743A1 Systems and Methods for PLL Linearity Measurement, PLL Output Duty Cycle Measurement and Duty Cycle Correction 失效
标题翻译： PLL线性度测量，PLL输出占空比测量和占空比校正的系统和方法
公开(公告)号：US20090146743A1
公开(公告)日：2009-06-11
申请号：US11952706
申请日：2007-12-07
申请人： Masaaki Kaneko , David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： Masaaki Kaneko , David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03L7/085 , H03L7/08
CPC分类号： H03L7/08
摘要： Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%.
摘要翻译：用于确定锁相环电路（PLL）中的压控振荡器（VCO）线性度，占空比确定和占空比校正的系统和方法一个实施例包括一种方法，包括以下步骤：将PLL的VCO的频率响应确定为占空比的功能，将基于VCO输出的信号施加到VCO输入，测量VCO输出信号的最终频率，确定对应于测量频率的占空比，以及配置占空比校正单元校正占空比的VCO输出信号约为50％。确定VCO的频率响应可以包括对于0％和100％之间的几个不同占空比值的每一个，将VCO输入信号施加到VCO并确定VCO输出信号的对应频率。这也可以在0％和100％的占空比下完成。

48. 发明申请

US20090128206A1 Apparatus and Method for Obtaining Desired Phase Locked Loop Duty Cycle without Pre-Scaler 审中-公开
标题翻译：用于获得期望的锁相环占空比的装置和方法，无需预定标器
公开(公告)号：US20090128206A1
公开(公告)日：2009-05-21
申请号：US11942983
申请日：2007-11-20
申请人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi
IPC分类号： H03K5/04 , H03L7/099
CPC分类号： H03K3/017 , H03L7/0995
摘要： An apparatus and method for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler are provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit.
摘要翻译：提供了一种用于在没有预定标器的情况下获得期望的锁相环（PLL）占空比的装置和方法。说明性实施例的PLL电路利用在VCO上同时工作的两个单独的环路。一个环路确保频率和相位锁定，而另一个环路确保占空比锁定。 VCO被修改为具有附加的控制端口来调整占空比。因此，VCO具有用于执行频率调整的一个控制端口和用于占空比调整的一个控制端口。结果，可以使用说明性实施例的PLL电路的VCO来控制占空比和频率，以便实现任何期望的占空比输出，而不需要VCO预定标器电路或占空比校正电路。

49. 发明申请

US20090066424A1 Programmable Interpolative Voltage Controlled Oscillator with Adjustable Range 审中-公开
标题翻译：可编程内插电压控制振荡器，可调范围
公开(公告)号：US20090066424A1
公开(公告)日：2009-03-12
申请号：US11853905
申请日：2007-09-12
申请人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi
IPC分类号： H03L7/00
CPC分类号： H03L7/18 , H03L7/0998
摘要： A programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. With the VCO, programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of an inner sub-ring from the set of control inputs provided to programmable delay cells of a main ring of the VCO. The minimum frequency output of the VCO is governed by the main ring programmable delay cell strength with the maximum frequency output of the VCO being governed by a ratio of strengths of the main ring programmable delay cells to the inner sub-ring programmable delay cell. By modifying the control inputs to the inner sub-ring and main ring programmable delay cells, the minimum and maximum frequency outputs, and thus the range between these two frequency outputs, are made programmable.
摘要翻译：提供了具有可调频率范围输出的可编程内插压控振荡器（VCO）。利用VCO，可以利用基于可编程延迟单元的控制输入来修改尺寸的可编程延迟单元。从提供给VCO的主环的可编程延迟单元的控制输入的集合可以向内部子环的可编程延迟单元提供不同的一组控制输入。 VCO的最小频率输出由主环路可编程延迟单元强度控制，VCO的最大频率输出由主环可编程延迟单元与内部子环可编程延迟单元的强度比控制。通过修改内部子环和主环可编程延迟单元的控制输入，可以将最小和最大频率输出，从而将这两个频率输出之间的范围编程为可编程。

50. 发明申请

US20080229270A1 Design Structure for a Duty Cycle Correction Circuit 有权
标题翻译：一种占空比校正电路的设计结构
公开(公告)号：US20080229270A1
公开(公告)日：2008-09-18
申请号：US12128754
申请日：2008-05-29
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F17/50 , H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00058 , H03K2005/00221
摘要： A design structure for a Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.
摘要翻译：提供了一种用于占空比校正（DCC）电路的设计结构，其中已知DCC电路拓扑中的场效应晶体管（FET）中的对被替换为与DCC电路的开关耦合的线性电阻器，使得当开关断开时，输入信号通过线性电阻器路由。线性电阻器比FET更容忍工艺，电压和温度（PVT）波动，因此，所得到的DCC电路与使用FET的已知DCC电路拓扑结构相比，具有PVT波动的DCC校正范围相对较小的变化。线性电阻器可以与开关并联设置并且与具有相对较大电阻值的一对FET串联。线性电阻器提供上拉或下拉输入信号的脉冲宽度的电阻，以便对输入信号的占空比提供校正。

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