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41. 发明授权

US5819051A Low speed serial bus protocol and circuitry 失效
公开(公告)号：US5819051A
公开(公告)日：1998-10-06
申请号：US578168
申请日：1995-12-29
申请人： David E. Murray , David R. Wooten
发明人： David E. Murray , David R. Wooten
IPC分类号： G06F13/42 , G06F13/00
CPC分类号： G06F13/4295
摘要： A serial bus communications method and circuitry for low speed serial bus functions. Over a two-wire communications channel, a unidirectional clock line and a bidirectional data line are used to transfer data. A protocol defines permissions, acknowledgments, terminations and retries handshaking between points. Circuitry is provided for reducing the latency of the serial bus when cooperating with the low speed functions. A resistive connection scheme is disclosed for converting high voltage signals into lower voltage signals.

42. 发明授权

US5651130A Memory controller that dynamically predicts page misses 失效
标题翻译：动态预测页面未命中的内存控制器
公开(公告)号：US5651130A
公开(公告)日：1997-07-22
申请号：US544109
申请日：1995-10-17
申请人： Lee B. Hinkle , Gary W. Thome , Paul A. Santeler , David R. Wooten , John A. Landry
发明人： Lee B. Hinkle , Gary W. Thome , Paul A. Santeler , David R. Wooten , John A. Landry
IPC分类号： G06F12/02 , G11C7/10 , G11C8/18 , G06F13/16
CPC分类号： G11C8/18 , G06F12/0215 , G11C7/1021
摘要： A memory controller dynamically predicts whether a next memory cycle which is not yet available will result in a page miss or page hit condition. RAS lines are selectively precharged if the next memory cycle is predicted to be a page miss. The memory controller keeps track of various combinations of types of cycles when a type of memory cycle is followed by a type of non-memory pending cycle. For each such combination, the memory controller determines the percentage of combinations which result in a page hit on the next memory cycle. Using this history, the memory controller selectively precharges the RAS lines when a certain combination of types of cycles indicates a percentage of hits is below a predicted threshold. If a number of page hits exceeds the predicted threshold, precharging is not performed.
摘要翻译：存储器控制器动态地预测下一个不可用的存储器周期是否会导致页错失或页命中条件。如果下一个存储周期被预测为页错，RAS线将被选择性地预充电。当一种类型的非存储器未决循环之后，存储器控制器跟踪周期类型的各种组合。对于每个这样的组合，存储器控制器确定在下一个存储周期中导致页命中的组合的百分比。使用这个历史，存储器控制器当循环类型的某种组合指示命中的百分比低于预测阈值时选择性地预充电RAS线。如果多次页面命中超过预测阈值，则不执行预充电。

43. 发明授权

US4431927A MOS Capacitive bootstrapping trigger circuit for a clock generator 失效
标题翻译：用于时钟发生器的MOS电容自举触发电路
公开(公告)号：US4431927A
公开(公告)日：1984-02-14
申请号：US256590
申请日：1981-04-22
申请人： Sargent S. Eaton, Jr. , David R. Wooten
发明人： Sargent S. Eaton, Jr. , David R. Wooten
IPC分类号： H03K19/096 , H03K5/02 , H03K17/06 , H03K19/017 , H03K17/12 , H03K5/135
CPC分类号： H03K19/01735
摘要： A trigger circuit is described for use in an MOS clock generator. The clock generator is the type which uses a conventional double bootstrapping circuit coupled to a control transistor to develop a high level clock output signal. The trigger circuit preconditions the control transistor to facilitate proper bootstrapping operation. Included in the trigger circuit is a plurality of interconnected transistors which respond to a pre-charge signal and then a warmup signal for turning the control transistor off and then for establishing selected potentials at the electrodes of the control transistor to precondition it for bootstrapping. In response to a subsequent trigger signal, the trigger circuit enables the control transistor for developing a high level clock output signal.
摘要翻译：描述了用于MOS时钟发生器的触发电路。时钟发生器是使用耦合到控制晶体管的常规双自举电路来开发高电平时钟输出信号的类型。触发电路预先控制晶体管，以促进适当的引导操作。包括在触发电路中的是多个互连的晶体管，其响应于预充电信号，然后响应用于使控制晶体管关闭的预热信号，然后用于在控制晶体管的电极处建立选定的电位，以便先决条件用于自举。响应于随后的触发信号，触发电路使得控制晶体管能够开发高电平时钟输出信号。

44. 发明授权

US4344156A High speed data transfer for a semiconductor memory 失效
标题翻译：半导体存储器的高速数据传输
公开(公告)号：US4344156A
公开(公告)日：1982-08-10
申请号：US195729
申请日：1980-10-10
申请人： Sargent S. Eaton, Jr. , David R. Wooten
发明人： Sargent S. Eaton, Jr. , David R. Wooten
IPC分类号： G11C11/41 , G11C7/00 , G11C7/10 , G11C8/04 , G11C8/10 , G11C13/00
CPC分类号： G11C8/10 , G11C7/1033 , G11C8/04
摘要： A system is described for use in a semiconductor memory for rapidly transferring data between a plurality of successive memory locations and a data output buss. The system includes a plurality of data latches for storing data derived from successive locations in memory, and a corresponding plurality of serially coupled decoders, each associated with one of the data latches. In response to an address input, one decoder is enabled for causing its associated data latch to output its stored data to the data buss. The latter decoder then disables itself and enables the next decoder so that a second latch outputs its stored data. The process continues with each decoder disabling itself and enabling the next decoder so that the data latches are caused to sequentially output their stored data.
摘要翻译：描述了一种在半导体存储器中用于在多个连续存储器位置和数据输出总线之间快速传送数据的系统。该系统包括多个数据锁存器，用于存储从存储器中的连续位置导出的数据，以及相应的多个串行耦合解码器，每个解码器与数据锁存器之一相关联。响应于地址输入，一个解码器被使能以使其相关联的数据锁存器将其存储的数据输出到数据总线。后一个解码器然后禁用自身并启用下一个解码器，使得第二个锁存器输出其存储的数据。该过程继续，每个解码器禁用自身并启用下一个解码器，使得数据锁存器被依次输出其存储的数据。

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