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41. 发明申请

US20080181112A1 Methods and Apparatus for Controlling Latency Variation in a Packet Transfer Network 有权
标题翻译：用于控制分组传输网络中的延迟变化的方法和装置
公开(公告)号：US20080181112A1
公开(公告)日：2008-07-31
申请号：US11669559
申请日：2007-01-31
申请人： Juergen Beck , David P. Sonnier
发明人： Juergen Beck , David P. Sonnier
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04J3/0632 , H04L47/28 , H04L2012/6481 , H04L2012/6489
摘要： Methods and apparatus for controlling latency variation of packets received in a packet transfer network are provided. A plurality of packets is received at a network element of a receive node of the packet transfer network. A time-stamp is provided for each of the plurality of packets. An egress delay time is computed at a scheduler of the network element for each of the plurality of packets in accordance with each corresponding time-stamp to provide a substantially constant latency for the plurality of packets upon egression from the network element.
摘要翻译：提供了用于控制在分组传送网络中接收的分组的等待时间变化的方法和装置。在分组传送网络的接收节点的网元处接收多个分组。为多个分组中的每个分组提供时间戳。根据每个对应的时间戳，在网络元件的调度器针对每个多个分组计算出口延迟时间，以便在从网络元素出现时为多个分组提供基本上恒定的等待时间。

42. 发明授权

US07275117B2 Fast pattern processor including a function interface system 有权
标题翻译：快速图案处理器，包括功能界面系统
公开(公告)号：US07275117B2
公开(公告)日：2007-09-25
申请号：US11237274
申请日：2005-09-28
申请人： Victor A. Bennett , David A. Brown , Sean W. McGee , David P. Sonnier , Leslie Zsohar
发明人： Victor A. Bennett , David A. Brown , Sean W. McGee , David P. Sonnier , Leslie Zsohar
IPC分类号： G06F15/16 , G06F15/00
CPC分类号： G06F9/3851 , G06F9/30101 , H04L49/102 , H04L49/254 , H04L49/3018
摘要： A fast pattern processor having an internal function bus and an external function bus. In one embodiment, a fast pattern processor includes: (1) an internal function bus, (2) an external function bus, (3) a context memory having a block buffer and a argument signature register wherein the block buffer includes processing blocks associated with a protocol data unit (PDU), (4) a pattern processing engine, associated with the context memory, that performs pattern matching and (5) a function interface system having (5A) a controller arbitration subsystem and (5B) a dispatch subsystem.
摘要翻译：具有内部功能总线和外部功能总线的快速模式处理器。在一个实施例中，快速图案处理器包括：（1）内部功能总线，（2）外部功能总线，（3）具有块缓冲器和参数签名寄存器的上下文存储器，其中所述块缓冲器包括与协议数据单元（PDU），（4）与上下文存储器相关联的模式处理引擎，执行模式匹配;以及（5）具有（5A）控制器仲裁子系统和（5B）调度子系统的功能接口系统。

43. 发明授权

US07224681B2 Processor with dynamic table-based scheduling using multi-entry table locations for handling transmission request collisions 有权
标题翻译：具有基于动态表的调度的处理器，使用多表项位置来处理传输请求冲突
公开(公告)号：US07224681B2
公开(公告)日：2007-05-29
申请号：US10085223
申请日：2002-02-28
申请人： David B. Kramer , David P. Sonnier , Leslie Zsohar
发明人： David B. Kramer , David P. Sonnier , Leslie Zsohar
IPC分类号： H04B7/212 , H04L12/28 , H04L12/56
CPC分类号： H04L49/90 , H04L47/50 , H04L47/521 , H04L49/901 , H04L49/9063 , H04L49/9073
摘要： A processor includes scheduling circuitry for scheduling data blocks for transmission from a plurality of transmission elements. The scheduling circuitry has at least one time slot table accessible thereto, and is configured for utilization of the time slot table in scheduling the data blocks for transmission. The time slot table includes a plurality of locations, with each of the locations corresponding to a transmission time slot and being configurable for storing identifiers of at least two of the transmission elements. In an illustrative embodiment, a given one of the locations in the time slot table stores in a first portion thereof an identifier of a first one of the transmission elements that has requested transmission of a block of data in the corresponding time slot, and stores in a second portion thereof an identifier of a second one of the transmission elements that has requested transmission of a block of data in the corresponding time slot. Furthermore, additional transmission elements generating colliding requests for the given location can be linked between the first and second transmission elements using a linking mechanism. The use of multi-entry time slot table locations to accommodate collisions between transmission element requests considerably facilitates the maintenance of desired traffic shaping requirements.
摘要翻译：处理器包括用于调度用于从多个传输元件传输的数据块的调度电路。调度电路具有可访问的至少一个时隙表，并且被配置为在调度用于发送的数据块时利用该时隙表。时隙表包括多个位置，其中每个位置对应于传输时隙，并且可配置为存储至少两个传输元件的标识符。在说明性实施例中，时隙表中的给定一个位置在其第一部分中存储已经请求在相应时隙中发送数据块的第一个传输元件的标识符，并存储在其第二部分是已经请求在相应时隙中传输数据块的传输元件中的第二个的标识符。此外，产生对给定位置的冲突请求的附加传输元件可以使用链接机构在第一和第二传输元件之间链接。使用多入口时隙表位置来适应传输元件请求之间的冲突大大有助于维持所需的流量整形要求。

44. 发明授权

US07159219B2 Method and apparatus for providing multiple data class differentiation with priorities using a single scheduling structure 有权
标题翻译：使用单个调度结构来提供具有优先级的多个数据类别区分的方法和装置
公开(公告)号：US07159219B2
公开(公告)日：2007-01-02
申请号：US10037164
申请日：2001-12-21
申请人： Jian-Guo Chen , David P. Sonnier , Ambalavanar Arulambalam , David E. Clune
发明人： Jian-Guo Chen , David P. Sonnier , Ambalavanar Arulambalam , David E. Clune
IPC分类号： G06F9/46 , G06F11/00
CPC分类号： H04L47/58 , H04L47/50 , H04L47/521 , H04L47/6215 , H04L47/623
摘要： A scheduler for shared network resources implementing a plurality of user selectable data scheduling schemes within a single hardware device. The schemes include strict priority, priority for one class plus smooth deficit weighted round robin for the other classes, bandwidth limited strict priority and smooth deficit weighted round robin for all user classes. The network operator selects one of the four schemes by enabling or disabling certain bits in the hardware device.
摘要翻译：用于共享网络资源的调度器，其在单个硬件设备内实现多个用户可选数据调度方案。这些方案包括严格的优先级，一类优先级加上其他类的平滑缺省加权轮回，带宽限制严格优先级和所有用户类的平滑缺省加权轮询。网络运营商通过启用或禁用硬件设备中的某些位来选择四种方案之一。

45. 发明授权

US07111289B2 Method for implementing dual link list structure to enable fast link-list pointer updates 有权
公开(公告)号：US07111289B2
公开(公告)日：2006-09-19
申请号：US10026351
申请日：2001-12-21
申请人： Christopher Koob , David P. Sonnier
发明人： Christopher Koob , David P. Sonnier
IPC分类号： G06F9/44
CPC分类号： G06F12/023
摘要： A method is disclosed for free memory allocation in a linked list memory scheme. Free lists are link lists designating available memory for data storage. This method leverages the ability to read memory while concurrently updating a pointer to the next location. Multiple free lists are used to reduce the number of cycles necessary to allocate memory. The number of entries in each free list is tracked. When memory becomes available, it is spliced into the shortest free list to achieve balance between the free lists. The free list structure disclosed consists of head, head +1, and tail pointers where head +1 is the next logical address pointed to from the head pointer location. The free list consists only of the head and tail pointers. Each link list structure of memory to be freed contains the head, head +1, and tail pointers. This allows us to simultaneously allocate and free with only 1 memory cycle. This structure provides the ability to free and allocate memory for further processing without executing the allocate step. A whole logical data packet can be spliced into a free list in one processing cycle. Utilization of the dual link lists reduces the bandwidth requirements for free memory allocation. Balancing of these dual lists is achieved by splicing a freed block of memory into the shortest list. The splicing method disclosed also reduces the processing cycles necessary to allocate and free memory.

46. 发明授权

US07000034B2 Function interface system and method of processing issued functions between co-processors 失效
公开(公告)号：US07000034B2
公开(公告)日：2006-02-14
申请号：US09798454
申请日：2001-03-02
申请人： Victor A. Bennett , David A. Brown , Sean W. McGee , David P. Sonnier , Leslie Zsohar
发明人： Victor A. Bennett , David A. Brown , Sean W. McGee , David P. Sonnier , Leslie Zsohar
IPC分类号： G06F15/16 , G06F15/20 , G06F15/76
CPC分类号： G06F9/3851 , G06F9/30101 , H04L49/102 , H04L49/254 , H04L49/3018
摘要： A function interface system for use with a fast pattern processor having an internal function bus and an external function bus and a method of operating the same. In one embodiment, the function interface system includes a controller arbitration subsystem configured to process an issued function request received from at least one of the internal function bus and the external function bus and a dispatch subsystem configured to retrieve the issued function request and dispatch the issued function request to at least one associated co-processor via the controller arbitration subsystem.

47. 发明授权

US6151689A Detecting and isolating errors occurring in data communication in a multiple processor system 失效
标题翻译：检测和隔离在多处理器系统中的数据通信中发生的错误
公开(公告)号：US6151689A
公开(公告)日：2000-11-21
申请号：US762653
申请日：1996-12-09
申请人： David J. Garcia , William Patterson Bunton , John Deane Coddington , John C. Krause , Susan Stone Meredith , David P. Sonnier , William Joel Watson , Linda Ellen Zalzala
发明人： David J. Garcia , William Patterson Bunton , John Deane Coddington , John C. Krause , Susan Stone Meredith , David P. Sonnier , William Joel Watson , Linda Ellen Zalzala
IPC分类号： G06F11/00 , H02H3/05
CPC分类号： G06F11/1482 , G06F11/1625 , G06F11/1645 , G06F11/165 , G06F11/1658 , G06F11/1675 , G06F11/2007 , G06F11/202 , G06F11/1683 , G06F11/2097 , G06F2201/845
摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.
摘要翻译：多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过也互连子处理器系统的路由设备互连。任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信。 I / O设备和CPU之间的通信是分组消息。来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息数据包。 CPU和I / O设备可以写入或读取系统的CPU的存储器。存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个内存访问被拒绝。

48. 发明授权

US5983269A Method and apparatus for configuring routing paths of a network communicatively interconnecting a number of processing elements 失效
标题翻译：用于配置通信地互连多个处理元件的网络的路由路径的方法和装置
公开(公告)号：US5983269A
公开(公告)日：1999-11-09
申请号：US764115
申请日：1996-12-09
申请人： H. David Mattson , William J. Watson , David J. Garcia , David P. Sonnier
发明人： H. David Mattson , William J. Watson , David J. Garcia , David P. Sonnier
IPC分类号： H04L12/56 , H04L29/12 , G06F11/00
CPC分类号： H04L45/02 , H04L29/12009 , H04L61/00
摘要： A multiple processing system, comprises at least a pair of processor units communicatively connected to a number of peripheral devices through a network that includes routing devices interconnected to route information in the form of message packets sent between the processor units and peripheral devices. Data describing the topographical interconnections of the system elements is maintained with the system. A service processor accesses the data, determines therefrom the topographical interconnections forming the network, assigns addresses/identifications to the system elements, and configures the router devices to establish the most direct routes between system elements for message packets sent on the network.
摘要翻译：多处理系统包括至少一对通过网络通信地连接到多个外围设备的处理器单元，所述网络包括以处理器单元和外围设备之间发送的消息分组形式的路由信息互连的路由设备。使用系统维护描述系统元件的地形互连的数据。服务处理器访问数据，从而确定构成网络的地形互连，为系统元件分配地址/标识，并配置路由器设备，以在网络上发送的消息分组之间建立最直接的路由。

49. 发明授权

US09218290B2 Data caching in a network communications processor architecture 有权
标题翻译：数据缓存在网络通信处理器架构中
公开(公告)号：US09218290B2
公开(公告)日：2015-12-22
申请号：US13192187
申请日：2011-07-27
申请人： David P. Sonnier , David A. Brown , Charles Edward Peet, Jr.
发明人： David P. Sonnier , David A. Brown , Charles Edward Peet, Jr.
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0813 , G06F12/084 , G06F12/0884
摘要： Described embodiments provide for storing data in a local cache of one of a plurality of processing modules of a network processor. A control processing module determines presence of data stored in its local cache while concurrently sending a request to read the data from a shared memory and from one or more local caches corresponding to other of the plurality of processing modules. Each of the plurality of processing modules responds whether the data is located in one or more corresponding local caches. The control processing module determines, based on the responses, presence of the data in the local caches corresponding to the other processing modules. If the data is present in one of the local caches corresponding to one of the other processing modules, the control processing module reads the data from the local cache containing the data and cancels the read request to the shared memory.
摘要翻译：所描述的实施例提供将数据存储在网络处理器的多个处理模块之一的本地高速缓存中。控制处理模块确定存储在其本地高速缓存中的数据的存在，同时发送从共享存储器读取数据的请求以及与多个处理模块中的其他处理模块对应的一个或多个本地高速缓存。多个处理模块中的每一个响应数据是否位于一个或多个对应的本地高速缓存中。控制处理模块基于响应确定在与其他处理模块对应的本地高速缓存中的数据的存在。如果数据存在于对应于其他处理模块之一的本地缓存之一中，则控制处理模块从包含数据的本地高速缓存中读取数据，并将读取请求取消给共享存储器。

50. 发明授权

US09154421B2 Network based data traffic detection and control 有权
标题翻译：基于网络的数据流量检测和控制
公开(公告)号：US09154421B2
公开(公告)日：2015-10-06
申请号：US11443393
申请日：2006-05-30
申请人： David P. Sonnier
发明人： David P. Sonnier
IPC分类号： H04L12/54 , H04L12/801 , H04L12/813 , H04L12/815 , H04L12/853 , H04L12/851 , H04L12/841 , H04L12/24 , H04L12/26
CPC分类号： H04L47/10 , H04L41/142 , H04L43/0852 , H04L47/20 , H04L47/22 , H04L47/2416 , H04L47/2441 , H04L47/283
摘要： A network-based apparatus for imposing a minimum transmit latency on data packets of a prescribed data type on a network includes at least one processor. The processor is operative: (i) to receive a data packet of the prescribed data type; (ii) to determine an elapsed time since an arrival of the received data packet at the apparatus; (iii) when the elapsed time is equal to or greater than the minimum transmit latency, to transmit the data packet; and (iv) when the elapsed time is less than the minimum transmit latency, to wait an amount of time at least equal to a difference between the elapsed time and the minimum transmit latency and then to transmit the data packet. The apparatus further includes memory coupled to the processor, the memory being configurable for storing data utilized by the processor.
摘要翻译：一种用于在网络上规定的数据类型的数据分组上施加最小传输延迟的基于网络的装置包括至少一个处理器。处理器可操作：（i）接收规定数据类型的数据包; （ii）确定从接收到的数据分组到达设备以来经过的时间; （iii）当经过时间等于或大于最小发送时延时，发送数据包; 以及（iv）当经过时间小于最小发送时延时，等待至少等于经过时间与最小发送时延之间的差的时间量，然后发送数据包。该装置还包括耦合到处理器的存储器，该存储器可配置为存储由处理器使用的数据。

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