专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US06859065B2 Use of dangling partial lines for interfacing in a PLD 失效
标题翻译：使用悬挂的部分线路在PLD中进行接口
公开(公告)号：US06859065B2
公开(公告)日：2005-02-22
申请号：US10650465
申请日：2003-08-27
申请人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
发明人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
IPC分类号： H03K19/177 , G06F17/50
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/17736
摘要： A routing structure in a PLD is implemented in a staggered fashion. Routing lines that would otherwise be “partial” and dangling at a routing architecture boundary are driven, providing additional flexibility for routing signals to the PLD core from the boundaries.
摘要翻译： PLD中的路由结构以交错方式实现。否则将在路由架构边界“部分”和悬挂的路由线被驱动，为从边界向PLD核心路由信号提供了额外的灵活性。

42. 发明授权

US07185306B1 Method and apparatus for enhancing signal routability 有权
标题翻译：用于增强信号可路由性的方法和装置
公开(公告)号：US07185306B1
公开(公告)日：2007-02-27
申请号：US10915647
申请日：2004-08-09
申请人： Paul Leventis , David Cashman
发明人： Paul Leventis , David Cashman
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for enhancing signal routability within an integrated circuit is provided. The method initiates with examining an outer edge of a sequence of logical array blocks. The method includes identifying an undriven routing wire in a vicinity of the outer edge. An underutilized driver proximate to the undriven routing wire is also identified. Then, the underutilized driver is coupled to the undriven routing wire. A computer readable medium and an integrated circuit are also provided.
摘要翻译：提供了一种用于增强集成电路内的信号可路由性的方法。该方法通过检查逻辑阵列块序列的外边缘来启动。该方法包括识别外边缘附近的未驱动布线。还识别了靠近未驱动路线的未充分利用的驾驶员。然后，未充分利用的驱动器耦合到未驱动的布线。还提供了计算机可读介质和集成电路。

43. 发明授权

US07983880B1 Simultaneous switching noise analysis using superposition techniques 有权
标题翻译：使用叠加技术进行同步开关噪声分析
公开(公告)号：US07983880B1
公开(公告)日：2011-07-19
申请号：US12034400
申请日：2008-02-20
申请人： Joshua David Fender , Paul Leventis
发明人： Joshua David Fender , Paul Leventis
IPC分类号： G06G7/00
CPC分类号： G06F17/5036 , G06F17/504 , G06F2217/82
摘要： Extended linear superposition methods, computer program products and systems to calculate Simultaneous Switching Noise (SSN) on victim Input/Output (I/O) pins of an electronic component caused by aggressor I/O pins is provided. A method includes calculating the quiet output voltage on a victim pin caused by the power supply only, and then calculating an aggressor noise response induced on the victim pin caused by a single aggressor pin and the power supply. To calculate SSN for a combination of aggressors, the SSNs for the different aggressors are linearly combined, and then the effects of the power supply are discounted by using the calculated quiet output voltage. Additionally, a linear victim substitution model is introduced to replace a full buffer model for a victim pin with a resistor with different resistance values depending on the induced voltage. Further, an alternate transmission line model is introduced to simplify SSN simulations of transmission lines.
摘要翻译：提供扩展线性叠加方法，计算机程序产品和系统，用于计算由侵入者I / O引脚引起的电子元件的受害者输入/输出（I / O）引脚上的同时开关噪声（SSN）。一种方法包括计算仅由电源引起的受害者引脚上的安静输出电压，然后计算由单个攻击者引脚和电源引起的受害者引脚上的侵扰者噪声响应。为了计算攻击者组合的SSN，不同攻击者的SSN线性组合，然后使用计算出的静音输出电压对电源的影响进行折扣。另外，引入线性受害者替代模型，以根据感应电压用具有不同电阻值的电阻替代受害针的完整缓冲器模型。此外，引入替代传输线模型以简化传输线的SSN仿真。

44. 发明授权

US07218133B2 Versatile logic element and logic array block 有权
公开(公告)号：US07218133B2
公开(公告)日：2007-05-15
申请号：US11050111
申请日：2005-02-02
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Timothy Betz
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Timothy Betz
IPC分类号： H03K19/003
CPC分类号： H03K19/17764 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

45. 发明授权

US07132852B2 Routing architecture with high speed I/O bypass path 有权
标题翻译：具有高速I / O旁路路径的路由架构
公开(公告)号：US07132852B2
公开(公告)日：2006-11-07
申请号：US10825387
申请日：2004-04-14
申请人： William Bradley Vest , Paul Leventis
发明人： William Bradley Vest , Paul Leventis
IPC分类号： H03K19/173
CPC分类号： H03K19/17792 , H03K19/17736 , H03K19/17744
摘要： Improved routing architectures including one or more high speed input/output (I/O) bypass paths are provided for use in, for example, programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs). The output bypass paths add additional routing connections to the routing architecture, providing faster connections between the output of a logic element (LE) in the PLD and external circuitry. In one embodiment, an output bypass path is used for directly connecting the output of the LE to the input of an I/O multiplexer of an I/O block. In another embodiment, the output bypass path also bypasses the I/O multiplexer, providing a direct connection between the output of the LE and a bypass multiplexer of the I/O block. Also provided is an input bypass path which provides direct connections between an input buffer of the I/O block and an otherwise dangling conductor at the periphery of the PLD's routing architecture.
摘要翻译：提供了改进的路由架构，包括一个或多个高速输入/输出（I / O）旁路路径，用于例如可编程逻辑器件（PLD），例如现场可编程门阵列（FPGA）。输出旁路路径为路由架构添加了额外的路由连接，从而在PLD中的逻辑元件（LE）的输出与外部电路之间提供更快的连接。在一个实施例中，输出旁路路径用于将LE的输出直接连接到I / O块的I / O多路复用器的输入端。在另一个实施例中，输出旁路路径也绕过I / O多路复用器，提供LE的输出和I / O块的旁路多路复用器之间的直接连接。还提供了一种输入旁路路径，其提供I / O块的输入缓冲器与PLD路由架构外围的另一悬挂导体之间的直接连接。

46. 发明申请

US20050231236A1 Routing architecture with high speed I/O bypass path 有权
标题翻译：具有高速I / O旁路路径的路由架构
公开(公告)号：US20050231236A1
公开(公告)日：2005-10-20
申请号：US10825387
申请日：2004-04-14
申请人： William Vest , Paul Leventis
发明人： William Vest , Paul Leventis
IPC分类号： H03K19/177
CPC分类号： H03K19/17792 , H03K19/17736 , H03K19/17744
摘要： Improved routing architectures including one or more high speed input/output (I/O) bypass paths are provided for use in, for example, programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs). The output bypass paths add additional routing connections to the routing architecture, providing faster connections between the output of a logic element (LE) in the PLD and external circuitry. In one embodiment, an output bypass path is used for directly connecting the output of the LE to the input of an I/O multiplexer of an I/O block. In another embodiment, the output bypass path also bypasses the I/O multiplexer, providing a direct connection between the output of the LE and a bypass multiplexer of the I/O block. Also provided is an input bypass path which provides direct connections between an input buffer of the I/O block and an otherwise dangling conductor at the periphery of the PLD's routing architecture.
摘要翻译：提供了改进的路由架构，包括一个或多个高速输入/输出（I / O）旁路路径，用于例如可编程逻辑器件（PLD），例如现场可编程门阵列（FPGA）。输出旁路路径为路由架构添加了额外的路由连接，从而在PLD中的逻辑元件（LE）的输出与外部电路之间提供更快的连接。在一个实施例中，输出旁路路径用于将LE的输出直接连接到I / O块的I / O多路复用器的输入端。在另一个实施例中，输出旁路路径也绕过I / O多路复用器，提供LE的输出和I / O块的旁路多路复用器之间的直接连接。还提供了一种输入旁路路径，其提供I / O块的输入缓冲器与PLD路由架构外围的另一悬挂导体之间的直接连接。

47. 发明授权

US06653862B2 Use of dangling partial lines for interfacing in a PLD 有权
公开(公告)号：US06653862B2
公开(公告)日：2003-11-25
申请号：US10140911
申请日：2002-05-06
申请人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
发明人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
IPC分类号： H03K19177
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/17736
摘要： A routing structure in a PLD is implemented in a staggered fashion. Routing lines that would otherwise be “partial” and dangling at a routing architecture boundary are driven, providing additional flexibility for routing signals to the PLD core from the boundaries.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式