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41. 发明授权

US09006890B2 Solder in cavity interconnection structures 有权
标题翻译：腔互连结构中的焊接
公开(公告)号：US09006890B2
公开(公告)日：2015-04-14
申请号：US13740698
申请日：2013-01-14
申请人： Chuan Hu , Shawna M Liff , Gregory S Clemons
发明人： Chuan Hu , Shawna M Liff , Gregory S Clemons
IPC分类号： H01L23/48 , H05K1/18 , H01L23/00
CPC分类号： H01L24/17 , H01L21/563 , H01L23/3121 , H01L23/3142 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L2224/10126 , H01L2224/10135 , H01L2224/10156 , H01L2224/1131 , H01L2224/11332 , H01L2224/11334 , H01L2224/11849 , H01L2224/13021 , H01L2224/13111 , H01L2224/16111 , H01L2224/16113 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/1624 , H01L2224/2929 , H01L2224/73103 , H01L2224/73104 , H01L2224/73203 , H01L2224/73204 , H01L2224/81139 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81424 , H01L2224/81439 , H01L2224/81447 , H01L2224/81455 , H01L2224/81805 , H01L2224/81815 , H01L2224/83192 , H01L2924/00011 , H01L2924/00012 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H05K1/181 , H01L2924/01083 , H01L2924/00014
摘要： The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.
摘要翻译：本公开涉及制造微电子封装的领域，其中在沉积在第一基板上的电介质层中形成空腔以保持焊接互连之间的分离。在一个实施例中，空腔可以具有倾斜的侧壁。在另一个实施例中，焊膏可以沉积在空腔中，并且在加热时可以形成焊料结构。在其它实施例中，焊料结构可以放置在空腔中，或者可以形成在可以连接第一衬底的第二衬底上。在其它实施例中，可以在第一基板和第二基板上形成焊料结构。焊料结构可以用于通过与第二衬底上的接触焊盘或焊料结构的接触和回流来形成焊料互连。

42. 发明申请

US20140063761A1 OFF-PLANE CONDUCTIVE LINE INTERCONNECTS IN MICROELECTRONIC DEVICES 有权
标题翻译：微电子设备中的非平面导电线互连
公开(公告)号：US20140063761A1
公开(公告)日：2014-03-06
申请号：US13601704
申请日：2012-08-31
申请人： Chuan Hu
发明人： Chuan Hu
IPC分类号： H05K1/11 , H05K3/10 , H05K7/06
CPC分类号： H05K1/11 , H01L23/66 , H01L2924/0002 , H05K1/0216 , H05K1/024 , H05K1/025 , H05K3/002 , H05K3/0029 , H05K3/10 , H05K3/107 , H05K3/465 , H05K2201/0352 , H05K2201/09036 , H05K2203/058 , Y10T29/49162 , H01L2924/00
摘要： Off-plane conductive line interconnects may be formed in microelectronic devices. In one example, such as device includes a first set of metal conductive lines in a dielectric substrate at a first horizontal layer of the substrate, a second set of metal conductive lines in the substrate at the first horizontal layer of the substrate and vertically offset from the first set of metal lines, and a dielectric material insulating the metal lines from each other and the first horizontal layer from other horizontal layers. Vias in the dielectric material to connect both the first and second set of metal lines to metal lines at a second horizontal layer of the substrate.
摘要翻译：离平面导线互连可以形成在微电子器件中。在一个示例中，例如器件包括在衬底的第一水平层处的电介质衬底中的第一组金属导电线，在衬底的第一水平层处的第二组金属导电线，并且垂直偏离第一组金属线，以及电介质材料，使金属线彼此绝缘，并且第一水平层与其他水平层绝缘。电介质材料中的通孔将第一和第二组金属线连接到衬底的第二水平层处的金属线。

43. 发明申请

US20140048959A1 MICROELECTRONIC PACKAGE HAVING NON-COPLANAR, ENCAPSULATED MICROELECTRONIC DEVICES AND A BUMPLESS BUILD-UP LAYER 有权
标题翻译：具有非共振微电子器件的微电子封装和无阻建筑层
公开(公告)号：US20140048959A1
公开(公告)日：2014-02-20
申请号：US13994521
申请日：2012-06-08
申请人： Chuan Hu
发明人： Chuan Hu
IPC分类号： H01L23/29 , H01L23/00
CPC分类号： H01L23/298 , H01L21/561 , H01L21/568 , H01L23/295 , H01L23/3107 , H01L23/5389 , H01L24/03 , H01L24/24 , H01L24/73 , H01L24/82 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16145 , H01L2224/24137 , H01L2224/24145 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/73265 , H01L2224/73267 , H01L2224/82031 , H01L2224/82039 , H01L2224/92244 , H01L2224/97 , H01L2924/00014 , H01L2924/12042 , H01L2224/45099 , H01L2924/00012 , H01L2224/82 , H01L2924/00
摘要： A microelectronic package having an encapsulated substrate comprising a plurality of microelectronic devices encapsulated within an encapsulation material, wherein the encapsulated structure may have an active surface proximate the active surfaces of the plurality of microelectronic devices, and wherein at least one of the plurality of microelectronic devices may have a height greater than another of the plurality of microelectronic devices (e.g. non-coplanar), The microelectronic package further includes a bumpless build-up layer structure formed proximate the encapsulated structure active surface. The microelectronic package may also have an active surface microelectronic device positioned proximate the encapsulated structure active surface and in electrical contact with at least one of the plurality of microelectronic devices of the encapsulated substrate.
摘要翻译：一种微电子封装，其具有封装的衬底，其包括封装在封装材料内的多个微电子器件，其中所述封装结构可具有靠近所述多个微电子器件的有源表面的有源表面，并且其中所述多个微电子器件中的至少一个可以具有大于多个微电子器件中的另一个（例如，非共面）的高度。微电子封装还包括在封装结构有源表面附近形成的无扰性积聚层结构。微电子封装还可以具有位于封装结构有源表面附近并与封装衬底的多个微电子器件中的至少一个电接触的有源表面微电子器件。

44. 发明申请

US20100320576A1 Die-warpage compensation structures for thinned-die devices, and methods of assembling same 有权
标题翻译：薄型模具装置的模翘曲补偿结构及其组装方法
公开(公告)号：US20100320576A1
公开(公告)日：2010-12-23
申请号：US12456638
申请日：2009-06-18
申请人： Chuan Hu
发明人： Chuan Hu
IPC分类号： H01L23/31 , H01L21/302
CPC分类号： H01L23/3114 , H01L21/6835 , H01L21/6836 , H01L23/3677 , H01L23/433 , H01L23/562 , H01L24/16 , H01L24/28 , H01L24/31 , H01L2221/68327 , H01L2221/68372 , H01L2224/16225 , H01L2224/73253 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/14 , H01L2924/1433 , H01L2924/16152
摘要： A back-side lamination (BSL) is applied after thinning a microelectronic die. The BSL is configured to be a thermal-expansion complementary structure to a metal wiring interconnect layout that is disposed on the active side of the microelectronic die.
摘要翻译：在微电子管芯变薄后应用背面层压（BSL）。 BSL被配置为与设置在微电子管芯的有源侧上的金属布线互连布局的热膨胀互补结构。

45. 发明授权

US07531429B2 Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices 有权
标题翻译：用于制造用于集成电路器件的超薄器件层的方法和装置
公开(公告)号：US07531429B2
公开(公告)日：2009-05-12
申请号：US11397412
申请日：2006-04-03
申请人： Peter Tolchinsky , Irwin Yablok , Chuan Hu , Richard D. Emery
发明人： Peter Tolchinsky , Irwin Yablok , Chuan Hu , Richard D. Emery
IPC分类号： H01L21/46 , H01L21/30 , H01L21/76 , H01L21/00 , H01L21/762
CPC分类号： H01L21/6835 , H01L21/3063 , H01L21/76254 , H01L23/367 , H01L24/81 , H01L2221/68359 , H01L2221/68368 , H01L2224/16 , H01L2224/73204 , H01L2224/81801 , H01L2924/01019 , H01L2924/14 , H01L2924/181 , Y10S438/96 , H01L2924/00012 , H01L2924/00
摘要： Embodiments of the invention use silicon on porous silicon wafers to produce a reduced-thickness IC device wafers. After device manufacturing, a temporary support is bonded to the device layer. The uppermost silicon layer is then separated from the silicon substrate by splitting the porous silicon layer. The porous silicon layer and temporary support are then removed and packaging is completed. Embodiments of the invention provide reliable, low cost methods and apparatuses for producing reduced-thickness IC device wafers to substantially increase thermal conductivity between the device layer of an IC device and a heat sink. In alternative embodiments, the layered silicon substrate includes an insulator layer on a layer of porous silicon and a silicon layer on the insulator layer.
摘要翻译：本发明的实施例在多孔硅晶片上使用硅来制造厚度较薄的IC器件晶片。在器件制造之后，临时支撑件被结合到器件层。然后通过分离多孔硅层将最上层的硅层与硅衬底分离。然后去除多孔硅层和临时支撑物，并且完成包装。本发明的实施例提供了可靠的，低成本的方法和装置，用于生产较薄的IC器件晶片，以显着增加IC器件的器件层与散热片之间的热导率。在替代实施例中，分层硅衬底包括在多孔硅层上的绝缘体层和绝缘体层上的硅层。

46. 发明申请

US20080277779A1 Microelectronic package and method of manufacturing same 审中-公开
标题翻译：微电子封装及其制造方法相同
公开(公告)号：US20080277779A1
公开(公告)日：2008-11-13
申请号：US11800686
申请日：2007-05-07
申请人： Abhishek Gupta , Zhiyong Wang , Chuan Hu
发明人： Abhishek Gupta , Zhiyong Wang , Chuan Hu
IPC分类号： H01L23/34 , H01L21/58 , H01L23/36
CPC分类号： H01L23/473 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/73253 , H01L2924/00014 , H01L2924/01079 , H01L2924/01327 , H01L2924/10253 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A microelectronic package comprises a substrate (110), a die (120) having a front side (121) and a back side (122) located over the substrate, a thermally conducting layer (130) on the back side of the die, a microchannel (140) above the thermally conducting layer, and a cap (150) on the microchannel. The thermally conducting layer between the die and the microchannel may lend mechanical strength to the package, may be thin enough to be compliant and avoid contributing meaningful CTE mismatch with the die, and may prevent the formation or propagation of cracks in the microchannel.
摘要翻译：微电子封装包括衬底（110），具有位于衬底上方的前侧（121）和后侧（122）的管芯（120），位于管芯背面的导热层（130），在导热层上方的微通道（140）和微通道上的盖（150）。管芯和微通道之间的导热层可以对包装提供机械强度，可以足够薄以使其顺从并且避免与管芯产生有意义的CTE失配，并且可以防止微通道中的裂纹的形成或扩展。

47. 发明授权

US07259965B2 Integrated circuit coolant microchannel assembly with targeted channel configuration 有权
标题翻译：具有目标通道配置的集成电路冷却液微通道组件
公开(公告)号：US07259965B2
公开(公告)日：2007-08-21
申请号：US11101061
申请日：2005-04-07
申请人： Je-Young Chang , Ioan Sauciuc , Chuan Hu , Chia-Pin Chiu , Gregory M. Chrysler , Ravi S. Prasher , Rajiv K. Mongia , Himanshu Pokharna , Eric DiStefano
发明人： Je-Young Chang , Ioan Sauciuc , Chuan Hu , Chia-Pin Chiu , Gregory M. Chrysler , Ravi S. Prasher , Rajiv K. Mongia , Himanshu Pokharna , Eric DiStefano
IPC分类号： H05K7/20
CPC分类号： H01L23/473 , F28F3/12 , F28F2260/02 , H01L2924/0002 , H01L2924/00
摘要： A microchannel structure has microchannels formed therein. The microchannels are to transport a coolant and to be proximate to an integrated circuit to transfer heat from the integrated circuit to the coolant. At least one of the microchannels has a length extent and has a first section at a first location along the length extent and a second section at a second location along the length extent. The first section of the microchannel has a first aspect ratio and the second section is divided into at least two sub-channels. Each sub-channel has a respective second aspect ratio that is greater than the first aspect ratio.
摘要翻译：微通道结构中形成有微通道。微通道将输送冷却剂并靠近集成电路以将热量从集成电路传递到冷却剂。微通道中的至少一个具有长度范围，并且具有沿着长度范围的第一位置处的第一部分和沿着长度范围的第二位置处的第二部分。微通道的第一部分具有第一宽高比，第二部分被划分为至少两个子通道。每个子通道具有大于第一宽高比的相应的第二宽高比。

48. 发明申请

US20060139883A1 Electronic packages, assemblies, and systems with fluid cooling and associated methods 有权
标题翻译：具有流体冷却和相关方法的电子封装，组件和系统
公开(公告)号：US20060139883A1
公开(公告)日：2006-06-29
申请号：US11363865
申请日：2006-02-27
申请人： Chuan Hu , Ravi Mahajan
发明人： Chuan Hu , Ravi Mahajan
IPC分类号： H05K7/20 , G06F1/20
CPC分类号： H01L23/473 , H01L2924/0002 , Y10T29/4913 , H01L2924/00
摘要： To accommodate high power densities associated with high-performance integrated circuits, an integrated circuit (IC) package includes a heat-dissipating structure in which heat is dissipated from a surface of one or more dice to a heat spreader. The heat spreader has a fluid-conducting channel formed therein, and a fluid coolant may be circulated through the channel via a micropump. In an embodiment, the channel is located at or near a surface of the heat spreader, and a heat-generating IC is in thermal contact with the heat spreader. In an embodiment, the IC is a thinned die that is coupled to the heat spreader via a thinned thermal interface material. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
摘要翻译：为了适应与高性能集成电路相关联的高功率密度，集成电路（IC）封装包括散热结构，其中热量从一个或多个骰子的表面散发到散热器。散热器具有形成在其中的导流通道，并且流体冷却剂可以经由微型泵循环通过通道。在一个实施例中，通道位于散热器的表面处或附近，并且发热IC与散热器热接触。在一个实施例中，IC是经由变薄的热界面材料耦合到散热器的薄化管芯。还描述了制造方法以及将包装应用于电子组件和电子系统。

49. 发明申请

US20060107988A1 Densely packed thermoelectric cooler 有权
公开(公告)号：US20060107988A1
公开(公告)日：2006-05-25
申请号：US10996195
申请日：2004-11-22
申请人： Chuan Hu , David Chau
发明人： Chuan Hu , David Chau
IPC分类号： H01L35/34 , H01L35/28 , H01L37/00
CPC分类号： H01L35/34 , H01L23/38 , H01L35/32 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention provide a thin film thermoelectric cooler. The cooler may have a high packing density that provides good cooling performance. The cooler may be formed by forming a first set of cooling elements, depositing a conformal insulating layer on the first set, then forming a second set of cooling elements between the first set of elements.

50. 发明授权

US07012011B2 Wafer-level diamond spreader 失效
公开(公告)号：US07012011B2
公开(公告)日：2006-03-14
申请号：US10876511
申请日：2004-06-24
申请人： Gregory M. Chrysler , Chuan Hu
发明人： Gregory M. Chrysler , Chuan Hu
IPC分类号： H01I21/00
CPC分类号： H01L21/4882 , H01L21/78 , H01L23/3732 , H01L23/3735 , H01L2224/0401 , H01L2224/04026 , H01L2224/16225 , H01L2224/16227 , H01L2224/274 , H01L2224/73253 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/15312 , H01L2924/00
摘要： An embodiment of the present invention is a technique to heat spread at wafer level. A silicon wafer is thinned. A chemical vapor deposition diamond (CVDD) wafer processed. The CVDD wafer is bonded to the thinned silicon wafer to form a bonded wafer. Metallization is plated on back side of the CVDD wafer. The CVDD wafer is reflowed to flatten the back side.

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