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41. 发明申请

US20050254180A1 MAGNETIC TUNNEL JUNCTION CAP STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：磁性隧道结结构及其形成方法
公开(公告)号：US20050254180A1
公开(公告)日：2005-11-17
申请号：US10709573
申请日：2004-05-14
申请人： Sivananda Kanakasabapathy , David Abraham , Ulrich Klostermann
发明人： Sivananda Kanakasabapathy , David Abraham , Ulrich Klostermann
IPC分类号： G11B5/33 , H01L43/12
CPC分类号： H01L43/12
摘要： A a magnetic random access memory (MRAM) device includes a cap layer formed over a magnetic tunnel junction (MTJ) stack layer, an etch stop layer formed over the first cap layer, and a hardmask layer formed over the etch stop layer. The etch stop layer is selected from a material such that an etch chemistry used for removing the hardmask layer has selectivity against etching the etch stop layer material.
摘要翻译：磁性随机存取存储器（MRAM）器件包括形成在磁隧道结（MTJ）堆叠层上的覆盖层，形成在第一覆盖层上的蚀刻停止层，以及形成在蚀刻停止层上的硬掩模层。蚀刻停止层选自材料，使得用于去除硬掩模层的蚀刻化学性质对蚀刻停止层材料的蚀刻具有选择性。

42. 发明申请

US20050105355A1 Method for homogeneously magnetizing an exchange-coupled layer system of a digital magnetic memory location device 失效
标题翻译：用于均匀地磁化数字磁存储器定位装置的交换耦合层系统的方法
公开(公告)号：US20050105355A1
公开(公告)日：2005-05-19
申请号：US10495301
申请日：2002-10-08
申请人： Hubert Brueckl , Ulrich Klostermann , Joachim Wecker
发明人： Hubert Brueckl , Ulrich Klostermann , Joachim Wecker
IPC分类号： G11C11/15 , G11C11/16 , H01F10/16 , H01F10/32 , H01F41/30 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C7/00
CPC分类号： B82Y25/00 , B82Y40/00 , G11C11/15 , G11C11/16 , H01F10/3272 , H01F41/304
摘要： A method and apparatus are described for homogeneously magnetizing an exchange-coupled layer system of a digital magnetic memory cell device comprising an AAF layer system and an antiferromagnetic layer that exchange-couples a layer of the AAF layer system, characterized in that, given a defined direction of magnetization of the antiferromagnetic layer, the magnetic layers of the AAF layer system are saturated in a magnetic field and, afterward, the position of the direction of the antiferromagnetic layer magnetization and the direction of the saturating magnetic field relative to one another is changed, so that they are at an angle α of 0°
摘要翻译：描述了用于均匀地磁化包括AAF层系统和反铁磁层的数字磁存储器单元装置的交换耦合层系统的方法和装置，所述AAF层系统和反铁磁层交换耦合一层AAF层系统，其特征在于，反铁磁层的磁化方向，AAF层系统的磁性层在磁场中饱和，之后，反铁磁性层的磁化方向和饱和磁场的方向相对于彼此的位置发生变化，使得它们相对于彼此成为0°<α<180°的角度α，之后关闭饱和磁场。

43. 发明授权

US08665629B2 Condensed memory cell structure using a FinFET 有权
标题翻译：使用FinFET的冷凝存储单元结构
公开(公告)号：US08665629B2
公开(公告)日：2014-03-04
申请号：US11864575
申请日：2007-09-28
申请人： Human Park , Ulrich Klostermann , Rainer Leuschner
发明人： Human Park , Ulrich Klostermann , Rainer Leuschner
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , H01L27/2436 , H01L29/66795 , H01L29/785
摘要： An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure.
摘要翻译：对集成电路的集成电路及其制造方法进行说明。在一个实施例中，集成电路包括包括电阻率变化存储元件的存储单元。电阻率变化存储元件电耦合到选择晶体管，该选择晶体管包括在源极和漏极之间形成在衬底表面上方的源极，漏极和鳍状结构的FinFET。翅片结构包括在基本上平行于衬底的表面的方向上延伸的沟道区，以及围绕沟道区的至少一部分形成的介电层，使得选择晶体管的有效沟道宽度至少部分依赖于翅片结构的高度。

44. 发明授权

US08063394B2 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US08063394B2
公开(公告)日：2011-11-22
申请号：US12247763
申请日：2008-10-08
申请人： Dieter Andres , Rainer Bruchhaus , Ulrike Gruening-Von Schwerin , Ulrich Klostermann , Franz Kreupl , Michael Kund , Petra Majewski , Christian Ruester , Bernhard Ruf , Ralf Symanczyk , Klaus-Dieter Ufert
发明人： Dieter Andres , Rainer Bruchhaus , Ulrike Gruening-Von Schwerin , Ulrich Klostermann , Franz Kreupl , Michael Kund , Petra Majewski , Christian Ruester , Bernhard Ruf , Ralf Symanczyk , Klaus-Dieter Ufert
IPC分类号： H01L29/02
CPC分类号： H01L29/0665 , B82Y10/00 , G11C13/0004 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L29/0673 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1273 , H01L45/14 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/149 , H01L45/1675 , H01L45/1683
摘要： According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element.
摘要翻译：根据实施例，公开了包括多个电阻变化存储单元的集成电路。每个存储单元包括布置在第一电极和第二电极之间的第一电极，第二电极和电阻变化存储元件。第一电极的面向电阻改变存储元件的端部的前表面积小于面向电阻变化存储元件的第二电极的端部的前表面区域。

45. 发明授权

US07902616B2 Integrated circuit having a magnetic tunnel junction device and method 有权
标题翻译：具有磁隧道连接装置和方法的集成电路
公开(公告)号：US07902616B2
公开(公告)日：2011-03-08
申请号：US12164736
申请日：2008-06-30
申请人： Ulrich Klostermann , Franz Kreupl
发明人： Ulrich Klostermann , Franz Kreupl
IPC分类号： H01L29/82
CPC分类号： H01L43/10 , H01L27/226 , H01L43/08
摘要： An integrated circuit having a magnetic tunnel junction and method. One embodiment provides an integrated circuit having a magnetic tunnel junction is provided. The magnetic tunnel junction includes a barrier layer. The barrier layer includes carbon, pyrolytic carbon, or graphene, or graphite.
摘要翻译：具有磁性隧道结的集成电路及其方法。一个实施例提供了一种具有磁性隧道结的集成电路。磁性隧道结包括阻挡层。阻挡层包括碳，热解碳或石墨烯或石墨。

46. 发明授权

US07855435B2 Integrated circuit, method of manufacturing an integrated circuit, and memory module 有权
标题翻译：集成电路，集成电路的制造方法和存储器模块
公开(公告)号：US07855435B2
公开(公告)日：2010-12-21
申请号：US12047167
申请日：2008-03-12
申请人： Ulrich Klostermann , Rainer Leuschner
发明人： Ulrich Klostermann , Rainer Leuschner
IPC分类号： H01L23/48
CPC分类号： H01L43/08 , G11C11/15 , G11C11/1675
摘要： According to one embodiment of the present invention, an integrated circuit including a plurality of memory cells is provided. Each memory cell includes a resistivity changing memory element which includes a top electrode, a bottom electrode, and resistivity changing material being disposed between the top electrode and the bottom electrode. Each resistivity changing memory element is at least partially surrounded by a thermal insulating structure. The thermal insulating structures are arranged such that the dissipation of heat generated within the resistivity changing memory elements into the environment of the resistivity changing memory elements is lowered.
摘要翻译：根据本发明的一个实施例，提供了包括多个存储单元的集成电路。每个存储单元包括电阻率变化存储元件，其包括设置在顶部电极和底部电极之间的顶部电极，底部电极和电阻率变化材料。每个电阻率变化记忆元件至少部分地被绝热结构包围。热绝缘结构被布置成使得在电阻率变化的存储元件内产生的热量消耗到电阻率变化存储元件的环境中降低。

47. 发明授权

US07663198B2 Magnetoresistive random access memory device with alternating liner magnetization orientation 失效
标题翻译：磁阻随机存取存储器件具有交替的线性磁化方向
公开(公告)号：US07663198B2
公开(公告)日：2010-02-16
申请号：US11512066
申请日：2006-08-29
申请人： Ulrich Klostermann
发明人： Ulrich Klostermann
IPC分类号： G11C11/15 , H01L21/8246
CPC分类号： H01L27/222 , H01L43/08
摘要： An arrangement of magnetic liners for the bit lines or word lines of an MRAM device that reduces or eliminates stray magnetic fields at the ends of the magnetic liners, thereby reducing the occurrence of offset fields over portions of the MRAM device due to the magnetic liners is described. The orientation of magnetization of adjacent magnetic liners is alternated, causing the end poles of the magnetic liners to cancel each other. The shapes of the ends of the magnetic liners are alternated to vary their switching fields. Methods are described that use this ability to vary the switching fields to alternate the orientation of magnetization of the magnetic liners.
摘要翻译：用于MRAM装置的位线或字线的磁性衬垫的布置，其减少或消除磁性衬垫的端部处的杂散磁场，从而减少由于磁性衬垫而导致的MRAM器件的部分上的偏移场的出现，描述。相邻磁性衬垫的磁化方向交替变化，导致磁性衬垫的端极彼此抵消。磁性衬垫的端部的形状被交替以改变其切换场。描述了使用这种能力来改变切换场以交替磁性衬垫的磁化方向的方法。

48. 发明授权

US07630231B2 Hybrid memory cell for spin-polarized electron current induced switching and writing/reading process using such memory cell 有权
标题翻译：用于自旋极化电子电流的混合存储单元使用这种存储单元感应开关和写入/读取过程
公开(公告)号：US07630231B2
公开(公告)日：2009-12-08
申请号：US11845525
申请日：2007-08-27
申请人： Jacques Miltat , Yoshinobu Nakatani , Ulrich Klostermann
发明人： Jacques Miltat , Yoshinobu Nakatani , Ulrich Klostermann
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A magnetoresistive hybrid memory cell includes first and second stacked structures. The first stacked structure includes a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship separated by a layer of non-magnetic material, wherein the first magnetic region has a fixed first magnetic moment vector and the second magnetic region has a free second magnetic moment vector that is switchable between the same and opposite directions with respect to the fixed first magnetic moment vector. The second stacked structure is at least partly arranged in a lateral relationship with respect to the first stacked structure and includes a third magnetic region having a fixed third magnetic moment vector and the second magnetic region. The first and second structures are arranged between at least two electrodes in electrical contact therewith.
摘要翻译：磁阻混合存储单元包括第一和第二堆叠结构。第一堆叠结构包括磁隧道结，该磁隧道结包括由非磁性材料层隔开的平行的叠置关系堆叠的第一和第二磁区，其中第一磁区具有固定的第一磁矩矢量，第二磁区具有相对于固定的第一磁矩矢量可在相同和相反方向之间切换的自由的第二磁矩矢量。第二堆叠结构至少部分地相对于第一堆叠结构布置在横向关系中，并且包括具有固定的第三磁矩矢量和第二磁性区域的第三磁性区域。第一和第二结构布置在与其接触的至少两个电极之间。

49. 发明授权

US07602637B2 Integrated circuits; methods for operating an integrating circuit; memory modules 失效
标题翻译：集成电路; 用于操作积分电路的方法; 内存模块
公开(公告)号：US07602637B2
公开(公告)日：2009-10-13
申请号：US11856643
申请日：2007-09-17
申请人： Ulrich Klostermann
发明人： Ulrich Klostermann
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/1675 , H01L27/222 , H01L43/08
摘要： Embodiments of the invention relate generally to integrated circuits, to methods for operating an integrating circuit, and to memory modules. In an embodiment of the invention, an integrated circuit having a magnetic random access memory cell is provided. The magnetic random access memory cell may include a reference layer structure being polarized in a first direction, a free layer structure including at least two anti-parallel coupled ferromagnetic layers and having an anisotropy in an axis parallel to the first direction, at least one of the at least two anti-parallel coupled ferromagnetic layers being made of a material having a temperature dependent saturation magnetization moment, and a non-magnetic tunnel barrier layer structure being disposed between the reference layer structure and the free layer structure.
摘要翻译：本发明的实施例一般涉及集成电路，用于操作积分电路的方法和存储器模块。在本发明的实施例中，提供了一种具有磁性随机存取存储单元的集成电路。磁性随机存取存储单元可以包括在第一方向上极化的参考层结构，包括至少两个反平行耦合的铁磁层并且在平行于第一方向的轴上具有各向异性的自由层结构，至少一个所述至少两个反平行耦合铁磁层由具有温度依赖性饱和磁化矩的材料制成，并且非磁性隧道势垒层结构设置在所述参考层结构和所述自由层结构之间。

50. 发明申请

US20090085121A1 Condensed Memory Cell Structure Using a FinFET 有权
标题翻译：使用FinFET的冷凝记忆单元结构
公开(公告)号：US20090085121A1
公开(公告)日：2009-04-02
申请号：US11864575
申请日：2007-09-28
申请人： Human Park , Ulrich Klostermann , Rainer Leuschner
发明人： Human Park , Ulrich Klostermann , Rainer Leuschner
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/228 , H01L27/2436 , H01L29/66795 , H01L29/785
摘要： An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure.
摘要翻译：对集成电路的集成电路及其制造方法进行说明。在一个实施例中，集成电路包括包括电阻率变化存储元件的存储单元。电阻率变化存储元件电耦合到选择晶体管，该选择晶体管包括在源极和漏极之间形成在衬底表面上方的源极，漏极和鳍状结构的FinFET。翅片结构包括在基本上平行于衬底的表面的方向上延伸的沟道区，以及围绕沟道区的至少一部分形成的介电层，使得选择晶体管的有效沟道宽度至少部分依赖于翅片结构的高度。

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