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41. 发明授权

US06586331B2 Low sheet resistance of titanium salicide process 有权
公开(公告)号：US06586331B2
公开(公告)日：2003-07-01
申请号：US09920604
申请日：2001-08-02
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L649
CPC分类号： H01L21/28052 , H01L21/28273 , H01L21/28518 , H01L29/665
摘要： A method for establishing low sheet resistance for the Titanium Salicide process that teaches a C-54 TiSix process by means of an additional vacuum bake. The present invention teaches an additional vacuum bake step prior to pre-metal HF dip during the Si-ion mixing process, an additional vacuum bake step prior to PAI during the PAI process, an additional vacuum bake step prior to pre-metal HF dip during the PAI process.

42. 发明授权

US06424021B1 Passivation method for copper process 有权
标题翻译：铜工艺钝化方法
公开(公告)号：US06424021B1
公开(公告)日：2002-07-23
申请号：US09607285
申请日：2000-06-30
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L2358
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/76801 , H01L21/76832 , H01L21/76834 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A composite dielectric layer and method of forming the composite dielectric layer for the passivation of exposed copper in a copper damascene structure are described. The composite layer consists of a passivation dielectric layer and an etch stop dielectric layer and is formed over the exposed copper prior to the deposit of an inter-metal or final passivating dielectric layer. Via holes are etched in the inter-metal or final passivating layer and the composite dielectric layer provides an etch stop function as well as passivation for the exposed copper conductor. A thin layer of passivation dielectric, such as silicon nitride, is formed directly over the exposed copper to passivate the copper. A thin layer of etch stop dielectric, such as silicon oxynitride, is then formed over the layer of passivation dielectric. The passivation dielectric is chosen for passivation properties and adhesion between the passivation dielectric and copper. The etch stop layer is chosen for etch stop properties. The composite layer is thinner than would be required if the layer of passivation dielectric also provided the etch stop function so that circuit capacitance is reduced by using the composite layer.
摘要翻译：描述了复合电介质层和形成用于钝化铜镶嵌结构中的暴露铜的复合介电层的方法。复合层由钝化电介质层和蚀刻停止介电层组成，并且在沉积金属间或最后的钝化介电层之前形成在暴露的铜上。在金属间或最后的钝化层中蚀刻通孔，并且复合介电层为暴露的铜导体提供蚀刻停止功能以及钝化。钝化电介质（例如氮化硅）的薄层直接形成在暴露的铜上以钝化铜。然后在钝化电介质层上形成薄层的蚀刻停止电介质，例如氮氧化硅。选择钝化电介质用于钝化性能和钝化电介质和铜之间的粘附。选择蚀刻停止层用于蚀刻停止性质。如果钝化电介质层还提供蚀刻停止功能，则复合层比所需要的薄，以便通过使用复合层减少电路电容。

43. 发明授权

US06353260B2 Effective diffusion barrier 有权
标题翻译：有效的扩散屏障
公开(公告)号：US06353260B2
公开(公告)日：2002-03-05
申请号：US09785106
申请日：2001-02-20
申请人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu
发明人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L2348
CPC分类号： H01L21/76856 , H01L21/76805 , H01L21/76843
摘要： In forming a semiconductor device in which an electrically conductive substrate is covered with a dielectric layer by the following steps, form a trench with a trench line on top and a contact hole on the bottom in the dielectric layer with the overall trench reaching down to the substrate. Preclean the trench. Form a tantalum film over the dielectric layer including the trench walls, covering the exposed the substrate surface. Fill grain boundaries of the tantalum film with at least one of tantalum oxide and tantalum nitride forming a filled tantalum film. Form a redeposited tantalum layer above the filled tantalum film. Form a copper seed film above the redeposited tantalum film. Plate the device filling the trench with a plated bulk copper layer on the seed film. Planarize the device to expose the top surface of the dielectric layer, removing surplus portions of the filled tantalum film, the copper seed film, and the bulk copper layer. The filled tantalum film is formed by exposing the tantalum to air under STP atmospheric conditions or by exposure to a nitrous oxide (N2O) gas in a plasma at a temperature of about 400° C.
摘要翻译：在通过以下步骤形成其中导电基板被电介质层覆盖的半导体器件中，在电介质层的顶部形成有沟槽线的沟槽和底部的接触孔，其中整个沟槽到达基质。清洁沟槽。在包括沟槽壁的电介质层上形成钽膜，覆盖暴露的衬底表面。用钽氧化物和氮化钽中的至少一种填充钽膜的晶界，形成填充的钽膜。在填充的钽膜上方形成再沉积的钽层。在再沉积的钽膜上方形成铜籽晶膜。将装有填充沟槽的装置用种子膜上的电镀体铜层铺平。平面化器件以暴露电介质层的顶表面，去除填充的钽膜，铜籽晶膜和块状铜层的剩余部分。填充的钽膜通过在STP大气条件下暴露于空气或通过在约400℃的温度下暴露于等离子体中的一氧化二氮（N 2 O）气体而形成。

44. 发明授权

US06326300B1 Dual damascene patterned conductor layer formation method 有权
标题翻译：双镶嵌图案导体层形成方法
公开(公告)号：US06326300B1
公开(公告)日：2001-12-04
申请号：US09157437
申请日：1998-09-21
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L214763
CPC分类号： H01L21/76825 , H01L21/31116 , H01L21/31138 , H01L21/31155 , H01L21/7681 , Y10S438/924
摘要： A method for forming through a dielectric layer a trench contiguous with a via. There is first provided a substrate having a contact region formed therein. There is then formed upon the substrate a blanket first dielectric layer. There is then formed upon the blanket first dielectric layer a blanket etch stop layer. There is then formed upon the blanket etch stop layer a patterned first photoresist layer which defines a location of a via to be formed through the blanket etch stop layer and the blanket first dielectric layer to access the contact region. There is then etched while employing a first etch method the blanket etch stop layer to form a patterned etch stop layer. There is then also implanted into the blanket first dielectric layer at the location of the via to be formed through the blanket first dielectric layer a dose of a first implanting ion to form a selectively ion implanted blanket first dielectric layer having an ion implanted region which etches more rapidly within a second etch method than an adjoining non ion implanted region of the selectively ion implanted blanket first dielectric layer. There is then formed over the patterned etch stop layer and the selectively ion implanted blanket first dielectric layer a blanket second dielectric layer. There is then formed upon the blanket second dielectric layer a patterned second photoresist layer which defines a location of a trench to be formed through the blanket second dielectric layer, where the trench has an areal dimension greater than the via and at least partially overlapping the via. Finally, there is then etched while employing the second etch method the trench through the blanket second dielectric layer and the via through the selectively ion implanted blanket first dielectric layer. There may then be formed within the trench and the via a contiguous patterned conductor interconnect layer and patterned conductor stud layer employing a damascene method.
摘要翻译：一种通过电介质层形成与通孔相邻的沟槽的方法。首先设置有形成有接触区域的基板。然后在衬底上形成第一绝缘层。然后在橡皮布第一介电层上形成覆盖层蚀刻停止层。然后在覆盖层蚀刻停止层上形成图案化的第一光致抗蚀剂层，其限定要通过覆盖层蚀刻停止层和覆盖层第一介电层形成的通孔的位置以访问接触区域。然后蚀刻，同时采用第一蚀刻方法，覆盖蚀刻停止层以形成图案化的蚀刻停止层。然后还在穿过第一介电层的通孔的位置处将橡皮布第一电介质层注入到第一介电层中，剂量为第一注入离子以形成具有离子注入区的选择性离子注入的第一介电层，其具有离子注入区在第二蚀刻方法中比选择性离子注入的第一介电层的邻接非离子注入区更快。然后在图案化的蚀刻停止层上形成有选择性地离子注入的第一介电层和第二绝缘层。然后在橡皮布的第二介电层上形成图案化的第二光致抗蚀剂层，该第二光致抗蚀剂层限定要穿过第二绝缘层形成的沟槽的位置，其中沟槽具有大于通孔的面积尺寸，并且至少部分地与通孔。最后，在采用第二蚀刻方法时，通过第二绝缘层和穿过选择性离子注入的第一介电层的通孔进行蚀刻。然后可以在沟槽和通孔内形成采用大马士革法的连续图案化导体互连层和图案化导体柱层。

45. 发明授权

US06277745B1 Passivation method of post copper dry etching 有权
标题翻译：后铜干蚀刻钝化法
公开(公告)号：US06277745B1
公开(公告)日：2001-08-21
申请号：US09221965
申请日：1998-12-28
申请人： Chung-Shi Liu , Shau-Lin Shue , Syun-Ming Jang , Chen-Hua Yu
发明人： Chung-Shi Liu , Shau-Lin Shue , Syun-Ming Jang , Chen-Hua Yu
IPC分类号： H01L2144
CPC分类号： H01L21/02071 , H01L21/321 , H01L21/32136 , H01L21/76841 , H01L21/7685 , H01L21/76852 , H01L21/76885
摘要： The present invention relates to a new structure and method for the passivation of copper electrical interconnects for the semiconductor industry. More particularly, the invention details a convenient method for completing the passivation of copper lines after they have been patterned by a dry etch process. The method includes the formation of a sandwich structure consisting of a bottom barrier layer, a copper layer and a top barrier layer. After the sandwich structure is patterned with a dry etch, for example, the resultant exposed copper sidewalls are then passivated by means of a barrier metal spacer process. The fully encapsulated copper lines are highly resistant to oxidation, which is an, otherwise, inherent problem associated with the lack of self passivation/exhibited by bare copper films.
摘要翻译：本发明涉及用于半导体工业的铜电互连钝化的新结构和方法。更具体地，本发明详细描述了在通过干蚀刻工艺对其进行图案化之后完成铜线钝化的方便方法。该方法包括形成由底部阻挡层，铜层和顶部阻挡层组成的夹层结构。在用干蚀刻图案化夹层结构之后，然后通过阻挡金属间隔物工艺钝化所得到的暴露的铜侧壁。完全封装的铜线具有很高的抗氧化性，这是另一种与裸铜膜缺乏自钝化/显示相关的固有问题。

46. 发明授权

US06177347B1 In-situ cleaning process for Cu metallization 有权
标题翻译： Cu金属化的原位清洗工艺
公开(公告)号：US06177347B1
公开(公告)日：2001-01-23
申请号：US09346527
申请日：1999-07-02
申请人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu
发明人： Chung-Shi Liu , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L2144
CPC分类号： H01L21/76814 , H01L21/76808 , H01L21/76843
摘要： A new method of in-situ cleaning in a copper metallization process is described. A copper line is provided overlying a first insulating layer on a semiconductor substrate. A silicon nitride layer is deposited overlying the copper line. A second insulating layer is deposited overlying the silicon nitride layer. A via is opened through the second insulating layer to the silicon nitride layer wherein a polymer forms on the sidewalls of the via. The silicon nitride layer within the via is removed wherein the copper line underlying the silicon nitride layer is exposed within the via and whereby the exposed copper line is oxidized forming a copper oxide layer within the via. The via is cleaned within a deposition chamber wherein the cleaning comprises the following steps: first sputtering Argon into the via to remove the polymer, second pumping down the deposition chamber, and third flowing H2 and He gases into the via to reduce the copper oxide layer to copper. Thereafter, a barrier metal layer is deposited onto the third insulating layer and within the via using the same deposition chamber and maintaining vacuum. A copper layer is formed within the via overlying the barrier metal layer to complete the copper metallization in the fabrication of an integrated circuit device.
摘要翻译：描述了一种在铜金属化过程中原位清洗的新方法。铜线设置在半导体衬底上的第一绝缘层上。沉积在铜线上的氮化硅层。沉积在氮化硅层上的第二绝缘层。将通孔穿过第二绝缘层打开到氮化硅层，其中在通孔的侧壁上形成聚合物。去除通孔内的氮化硅层，其中氮化硅层下面的铜线在通孔内暴露，由此暴露的铜线被氧化，形成通孔内的氧化铜层。在沉积室中清洁通孔，其中清洁包括以下步骤：首先将氩气溅射到通孔中以除去聚合物，第二次将沉积室泵送，并且将第三流动的H 2和He气体进入通孔以减少氧化铜层到铜。此后，使用相同的沉积室将阻挡金属层沉积到第三绝缘层和通孔内，并保持真空。在覆盖阻挡金属层的通孔中形成铜层，以在集成电路器件的制造中完成铜金属化。

47. 发明授权

US6150272A Method for making metal plug contacts and metal lines in an insulating layer by chemical/mechanical polishing that reduces polishing-induced damage 有权
标题翻译：通过化学/机械抛光在绝缘层中制造金属插头触点和金属线的方法，减少抛光引起的损伤
公开(公告)号：US6150272A
公开(公告)日：2000-11-21
申请号：US192456
申请日：1998-11-16
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L21/768 , H01L21/302 , H01L21/461
CPC分类号： H01L21/7684 , H01L21/76802
摘要： A method for making metal plugs in via holes and interconnections by an improved chem/mech polishing process using an organic protective layer is achieved. After devices are formed on a substrate which includes a patterned conducting layer, a low-k insulating layer is deposited and planarized. An organic protective layer, such as a polymer, is deposited, and contact holes are etched in the polymer and insulating layers. A thin Ti/TiN barrier layer is deposited and a tungsten metal is deposited sufficiently thick to fill the contact holes. The tungsten metal and barrier layers are chem/mech polished back to form metal plugs, while the protective layer protects the insulating layer from CMP scratching and other CMP defects. The organic protective layer is easily removed using plasma ashing and other cleaning steps. The method is also applicable to forming metal interconnections. Trenches are etched, over and to the metal plugs, in an insulating layer having an organic protective layer. A barrier layer is deposited and a highly conductive metal, such as AlCu alloy or Cu, is deposited and are chem/mech polished back to the protective layer. The protective layer is then removed to form the metal interconnections in the insulator.
摘要翻译：实现了通过使用有机保护层的改进的化学/机械抛光方法在通孔和互连中制造金属塞的方法。在器件形成在包括图案化导电层的衬底上之后，沉积低k绝缘层并进行平坦化。沉积有机保护层，如聚合物，并在聚合物和绝缘层中蚀刻接触孔。沉积薄的Ti / TiN阻挡层，并且将钨金属沉积得足够厚以填充接触孔。钨金属和阻挡层被化学/机械抛光以形成金属塞，而保护层保护绝缘层免受CMP划伤和其它CMP缺陷。使用等离子体灰化和其他清洁步骤容易地去除有机保护层。该方法也适用于形成金属互连。在具有有机保护层的绝缘层中，将沟槽蚀刻在金属插塞上方并附着在金属插塞上。沉积阻挡层，并沉积诸如AlCu合金或Cu的高导电性金属，并将其化学/机械抛光回保护层。然后去除保护层以在绝缘体中形成金属互连。

48. 发明授权

US6037258A Method of forming a smooth copper seed layer for a copper damascene structure 有权
标题翻译：形成铜镶嵌结构的光滑铜籽晶层的方法
公开(公告)号：US6037258A
公开(公告)日：2000-03-14
申请号：US307206
申请日：1999-05-07
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/76873 , H01L21/7684 , H01L21/76843 , H01L2221/1089
摘要： A method for fabricating a copper interconnect structure, in a damascene type opening, comprised a thick copper layer, obtained via an electro-chemical deposition procedure, and comprised of an underlying, copper seed layer, featuring a smooth top surface topography, has been developed. The smooth top surface topography, of the underlying copper seed layer, is needed to allow the voidless deposition of the overlying, thick copper layer, and is also needed to allow the deposition of the overlying thick copper layer to be realized, with a surface that can survive a chemical mechanical polishing procedure, without the risk of unwanted dishing or spooning phenomena. The desirable, copper seed layer, is obtained via a process sequence that features: a plasma vapor deposition of a first copper seed layer; an argon purge procedure; and a second plasma vapor deposition of a second copper seed layer. The use of an argon purge, allows the increase in temperature, introduced by plasma bombardment, to be decreased, allowing a copper seed layer, featuring a smooth top surface topography, to be obtained.
摘要翻译：已经开发了一种用于制造铜互连结构的方法，该镶嵌型开口包括通过电化学沉积程序获得的厚铜层，并且包括具有光滑顶表面形貌的底层铜种子层。需要底层铜种子层的平滑的顶表面形貌，以允许上覆的厚铜层的无空隙沉积，并且还需要允许实现覆盖的厚铜层的沉积，其表面可以在化学机械抛光程序中生存，不会有不希望的凹陷或勺子现象的风险。所需的铜种子层通过以下工艺顺序获得，其特征在于：第一铜种子层的等离子体气相沉积; 氩气清洗程序; 以及第二铜籽晶层的第二等离子体气相沉积。通过使用氩气吹扫，允许通过等离子体轰击引入的温度升高降低，从而获得具有光滑顶表面形貌的铜籽晶层。

49. 发明授权

US09536818B2 Semiconductor package and method of forming the same 有权
标题翻译：半导体封装及其形成方法
公开(公告)号：US09536818B2
公开(公告)日：2017-01-03
申请号：US13272434
申请日：2011-10-13
申请人： Wei-Hung Lin , Ming-Da Cheng , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
发明人： Wei-Hung Lin , Ming-Da Cheng , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
IPC分类号： H01L23/498 , B23K1/20 , H01L21/48 , H01L23/00
CPC分类号： H01L23/49894 , H01L21/4864 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05647 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/16238 , H01L2224/73204 , H01L2224/81022 , H01L2224/81191 , H01L2224/81815 , H01L2924/1305 , H01L2924/13091 , H01L2924/00014 , H01L2924/01073 , H01L2924/01049 , H01L2924/0105 , H01L2924/0103 , H01L2924/01025 , H01L2924/01024 , H01L2924/01022 , H01L2924/01032 , H01L2924/01038 , H01L2924/01078 , H01L2924/01012 , H01L2924/01013 , H01L2924/0104 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012 , H01L2924/01082 , H01L2924/01083 , H01L2924/01079 , H01L2924/01051 , H01L2924/04941 , H01L2924/04953 , H01L2924/00
摘要： A method of a semiconductor package includes providing a substrate having a conductive trace coated with an organic solderability preservative (OSP) layer, removing the OSP layer from the conductive trace, and then coupling a chip to the substrate to form a semiconductor package.
摘要翻译：半导体封装的方法包括提供具有涂覆有有机可焊性防腐剂（OSP）层的导电迹线的衬底，从导电迹线去除OSP层，然后将芯片耦合到衬底以形成半导体封装。

50. 发明授权

US09123553B2 Method and system for bonding 3D semiconductor device 有权
标题翻译：三维半导体器件接合方法及系统
公开(公告)号：US09123553B2
公开(公告)日：2015-09-01
申请号：US13269260
申请日：2011-10-07
申请人： Chung-Shi Liu , Chen-Hua Yu , Yuh-Jier Mii , Yuan-Chen Sun
发明人： Chung-Shi Liu , Chen-Hua Yu , Yuh-Jier Mii , Yuan-Chen Sun
IPC分类号： H01L21/00 , H01L25/065 , H01L21/683 , H01L21/768 , H01L23/00 , H01L25/00
CPC分类号： H01L21/50 , H01L21/6835 , H01L21/6836 , H01L21/762 , H01L21/76898 , H01L24/95 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/68354 , H01L2224/05553 , H01L2224/16 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/14 , H01L2924/00 , H01L2924/00014
摘要： A method and system and for fabricating 3D (three-dimensional) SIC (stacked integrated chip) semiconductor devices. The system includes a vacuum chamber, a vacuum-environment treatment chamber, and a bonding chamber, though in some embodiments the same physical enclosure may serve more than one of these functions. A vacuum-environment treatment source in communication with the vacuum-environment treatment chamber provides a selected one or more of a hydrogen (H2)-based thermal anneal, an H2-based plasma treatment, or an ammonia (NH3)-based plasma treatment. In another embodiment, a method includes placing a semiconductor chip in a vacuum environment, performing a selected vacuum-environment treatment, and bonding the chip to a base wafer. A plurality of chips formed as dice on a semiconductor wafer may, of course, be simultaneously treated and bonded in this way as well, either before or after dicing.
摘要翻译：一种用于制造3D（三维）SIC（堆叠集成芯片）半导体器件的方法和系统。该系统包括真空室，真空环境处理室和粘合室，尽管在一些实施例中，相同的物理外壳可以用于这些功能中的一种以上。与真空环境处理室连通的真空环境处理源提供基于氢（H 2）的热退火，基于H 2的等离子体处理或基于氨（NH 3）的等离子体处理中的一种或多种。在另一个实施例中，一种方法包括将半导体芯片放置在真空环境中，执行所选择的真空环境处理，以及将芯片接合到基底晶片。在半导体晶片上形成为多个芯片的多个芯片当然可以在切割之前或之后以这种方式同时进行处理和粘合。

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