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41. 发明申请

US20060050548A1 Semiconductor memory device capable of compensating for leakage current 有权
标题翻译：能够补偿漏电流的半导体存储器件
公开(公告)号：US20060050548A1
公开(公告)日：2006-03-09
申请号：US11220294
申请日：2005-09-06
申请人： Hyung-Rok Oh , Baek-Hyung Cho , Choong-Keun Kwak
发明人： Hyung-Rok Oh , Baek-Hyung Cho , Choong-Keun Kwak
IPC分类号： G11C11/00
CPC分类号： G11C7/12 , G11C7/14 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C2013/0054 , G11C2213/79
摘要： A semiconductor memory device compensates leakage current. A plurality of memory cells is disposed at intersections of word lines and bit lines. A plurality of dummy cells is connected to at least one dummy bit line. A leakage compensation circuit is connected to the at least one dummy bit line that outputs a leakage compensation current to at least one of the bit lines. A read current supply circuit outputs a read current necessary for a read operation to at least one of the bit lines in response to a first control signal. The memory device is a phase-change memory device containing phase-change material. The semiconductor memory device compensates leakage current in a read operation and supplies the leakage compensation current to a selected bit line, thereby suppressing error operation occurrence caused by leakage current.
摘要翻译：半导体存储器件补偿漏电流。多个存储单元设置在字线和位线的交点处。多个虚拟单元被连接到至少一个虚拟位线。泄漏补偿电路连接到至少一个虚拟位线，其向至少一个位线输出泄漏补偿电流。读取电流供应电路响应于第一控制信号向至少一个位线输出读取操作所需的读取电流。存储器件是包含相变材料的相变存储器件。半导体存储器件在读取操作中补偿漏电流，并将泄漏补偿电流提供给所选择的位线，从而抑制由漏电流引起的误操作发生。

42. 发明申请

US20050281106A1 Semiconductor memory device for low power consumption 有权
标题翻译：用于低功耗的半导体存储器件
公开(公告)号：US20050281106A1
公开(公告)日：2005-12-22
申请号：US11146513
申请日：2005-06-07
申请人： Gong-Heum Han , Choong-Keun Kwak , Joon-Min Park
发明人： Gong-Heum Han , Choong-Keun Kwak , Joon-Min Park
IPC分类号： G11C5/14 , G11C7/00 , G11C11/417
CPC分类号： G11C11/417 , G11C5/147
摘要： A semiconductor memory device, which has an array of memory cells connected with a plurality of bit line pairs and a plurality of word lines, to perform a read or write operation of data, having low power consumption is provided. The device includes a first power supply for supplying a first power source voltage. Also, a second power supply supplies a second power source voltage having a lower voltage level than the first power source voltage. Further, the device includes a standard ground. An elevated ground circuit provides an elevated ground voltage having a higher voltage level than that of the standard ground. A first power circuit is connected with the first power supply and the standard ground, and operates in response to the first power source voltage. A second power circuit is connected with the second power supply and the elevated ground circuit, and operates in response to the second power source voltage. Thereby, power and chip size can be reduced.
摘要翻译：提供具有与多个位线对和多个字线连接的存储单元的阵列以执行具有低功耗的数据的读取或写入操作的半导体存储器件。该装置包括用于提供第一电源电压的第一电源。此外，第二电源提供具有比第一电源电压低的电压电平的第二电源电压。此外，该装置包括标准接地。提升的接地电路提供比标准接地电压高的电压电平的升高的接地电压。第一电源电路与第一电源和标准接地相连接，并响应于第一电源电压而工作。第二电源电路与第二电源和升高的接地电路连接，并且响应于第二电源电压而工作。从而可以降低功率和芯片尺寸。

43. 发明授权

US06657264B2 Layout method of latch-up prevention circuit of a semiconductor device 有权
公开(公告)号：US06657264B2
公开(公告)日：2003-12-02
申请号：US09940733
申请日：2001-08-28
申请人： Beak-Hyung Cho , Choong-Keun Kwak
发明人： Beak-Hyung Cho , Choong-Keun Kwak
IPC分类号： H01L2994
CPC分类号： H01L27/0921 , H01L27/0266
摘要： A layout method is provided for a latch-up prevention circuit of a semiconductor memory device which includes the steps of: arranging a cell array at substantially the middle of the device; placing peripheral circuits next to both sides of the cell array; placing a plurality of pads on both sides of the cell array between the peripheral circuits and both edges of the device; and arranging guard rings beneath the plurality of pads. The layout method further includes a plurality of ESD protection transistors disposed axially along the direction as the plurality of pads between the plurality of pads and an edge of the device. And each of guard ring is a NWELL guard ring, and connected to a supply voltage and ground.

44. 发明授权

US5818770A Circuit and method for write recovery control 失效
标题翻译：用于写恢复控制的电路和方法
公开(公告)号：US5818770A
公开(公告)日：1998-10-06
申请号：US979302
申请日：1997-11-26
申请人： Jae-Chul Kim , Choong-Keun Kwak
发明人： Jae-Chul Kim , Choong-Keun Kwak
IPC分类号： G11C11/407 , G11C7/12 , G11C8/08 , G11C8/10 , G11C7/00
CPC分类号： G11C7/12 , G11C8/08 , G11C8/10
摘要： The present invention relates to a circuit and method for write recovery control for suppressing malfunctions during a write recovery operation. The circuit is for use in a semiconductor memory device including a plurality of memory cells connected in a matrix form to a plurality of word lines and paired bit lines. The circuit comprises a variable load circuit connected to the bit lines, for controlling the voltage level of the bit lines in response to a write enable signal, a word line selector for selecting a predetermined word line in response to an input address, and a delay controller for providing a delay control signal to the word line selector so as to delay activation of the word line selector during the write recovery operation.
摘要翻译：本发明涉及一种用于在写入恢复操作期间抑制故障的写恢复控制的电路和方法。该电路用于包括以矩阵形式连接到多条字线和成对位线的多个存储单元的半导体存储器件。电路包括连接到位线的可变负载电路，用于响应于写使能信号来控制位线的电压电平，用于响应于输入地址选择预定字线的字线选择器和延迟控制器，用于向字线选择器提供延迟控制信号，以便在写恢复操作期间延迟字线选择器的激活。

45. 发明授权

US07535760B2 Memory devices and memory systems having the same 有权
标题翻译：具有相同的存储器件和存储器系统
公开(公告)号：US07535760B2
公开(公告)日：2009-05-19
申请号：US11902424
申请日：2007-09-21
申请人： Kwang-Jin Lee , Won-Seok Lee , Choong-Keun Kwak
发明人： Kwang-Jin Lee , Won-Seok Lee , Choong-Keun Kwak
IPC分类号： G11C14/00
CPC分类号： H01L27/10802 , G11C7/00 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/1084 , G11C11/4063 , H01L21/84 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A non volatile memory device and a memory system having the same are disclosed. The non volatile memory device may include a memory cell array having a plurality of non volatile memory cells, a DRAM interface for exchanging data, a command and an address with an external device, a controller for selecting one of the memory cells in response to the address and performing a control operation for one of outputting data of the selected memory cell to the external device in response to the command and storing data received from the external device, and a DRAM buffer memory. The DRAM buffer memory has dynamic memory cells, and each of the dynamic memory cells has one transistor with a floating body.
摘要翻译：公开了一种非易失性存储器件和具有该非易失性存储器件的存储器系统。非易失性存储器件可以包括具有多个非易失性存储器单元的存储器单元阵列，用于交换数据的DRAM接口，与外部设备的命令和地址，用于响应于所述存储器单元选择所述存储器单元中的一个的控制器对所述存储器单元的数据的输出响应于所述命令并存储从所述外部设备接收的数据以及DRAM缓冲存储器，对所述存储单元的数据进行输出的地址和执行控制操作。 DRAM缓冲存储器具有动态存储单元，并且每个动态存储单元具有一个具有浮体的晶体管。

46. 发明授权

US07248494B2 Semiconductor memory device capable of compensating for leakage current 有权
标题翻译：能够补偿漏电流的半导体存储器件
公开(公告)号：US07248494B2
公开(公告)日：2007-07-24
申请号：US11220294
申请日：2005-09-06
申请人： Hyung-Rok Oh , Baek-Hyung Cho , Choong-Keun Kwak
发明人： Hyung-Rok Oh , Baek-Hyung Cho , Choong-Keun Kwak
IPC分类号： G11C11/00
CPC分类号： G11C7/12 , G11C7/14 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C2013/0054 , G11C2213/79
摘要： A semiconductor memory device compensates leakage current. A plurality of memory cells is disposed at intersections of word lines and bit lines. A plurality of dummy cells is connected to at least one dummy bit line. A leakage compensation circuit is connected to the at least one dummy bit line that outputs a leakage compensation current to at least one of the bit lines. A read current supply circuit outputs a read current necessary for a read operation to at least one of the bit lines in response to a first control signal. The memory device is a phase-change memory device containing phase-change material. The semiconductor memory device compensates leakage current in a read operation and supplies the leakage compensation current to a selected bit line, thereby suppressing error operation occurrence caused by leakage current.
摘要翻译：半导体存储器件补偿漏电流。多个存储单元设置在字线和位线的交点处。多个虚拟单元被连接到至少一个虚拟位线。泄漏补偿电路连接到至少一个虚拟位线，其向至少一个位线输出泄漏补偿电流。读取电流供应电路响应于第一控制信号向至少一个位线输出读取操作所需的读取电流。存储器件是包含相变材料的相变存储器件。半导体存储器件在读取操作中补偿漏电流，并将泄漏补偿电流提供给所选择的位线，从而抑制由漏电流引起的误操作发生。

47. 发明申请

US20050117388A1 WRITE DRIVER CIRCUIT IN PHASE CHANGE MEMORY DEVICE AND METHOD FOR APPLYING WRITE CURRENT 有权
标题翻译：相变存储器件中的写驱动电路和应用写入电流的方法
公开(公告)号：US20050117388A1
公开(公告)日：2005-06-02
申请号：US10969697
申请日：2004-10-20
申请人： Beak-Hyung Cho , Choong-Keun Kwak
发明人： Beak-Hyung Cho , Choong-Keun Kwak
IPC分类号： G11C13/02 , G11C13/00 , G11C16/02 , G11C16/12 , G11C16/30 , G11C29/02 , H01L27/105 , H01L45/00 , G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0038 , G11C29/02 , G11C29/028 , G11C2013/0078 , G11C2029/5006 , G11C2213/79
摘要： A write driver circuit including a plurality of programmable fuses for a phase change memory device in which a write operation is correctly performed even in the case where a current output shift in a write current generation circuit; or in the case where a phase change memory cell has a phase change property shift due to an external factor or due a process change. The write driver circuit includes; a write current control unit for outputting a first or second level of voltage selected, by selecting one of a first or second programmable current path, based on whether a first or second selection pulse signal is applied; and a current driving unit for generating a write current controlled by the output voltage of the write current control unit. Each of the first and second programmable current paths includes fuses that can be programmed to adjusted their resistance to adjust the respective selected output voltage to compensate for a current output shift in a write current generation circuit or for a phase change memory cell has a phase change property shift.
摘要翻译：一种写入驱动器电路，包括用于相变存储器件的多个可编程保险丝，其中即使在写入电流产生电路中的电流输出移位的情况下也正确地执行写入操作; 或者在相变存储单元由于外部因素或由于处理变化而具有相变特性偏移的情况。写驱动电路包括：写入电流控制单元，用于通过选择第一或第二可编程电流路径中的一个，基于是施加第一还是第二选择脉冲信号来输出所选择的第一或第二电平电平; 以及电流驱动单元，用于产生由写入电流控制单元的输出电压控制的写入电流。第一和第二可编程电流路径中的每一个包括熔丝，其可以被编程以调整其电阻以调整相应的选择的输出电压以补偿写入电流产生电路中的电流输出偏移，或者对于相变存储器单元具有相变财产转移

48. 发明授权

US06714463B2 Semiconductor memory device having reduced chip select output time 有权
标题翻译：具有减少芯片选择输出时间的半导体存储器件
公开(公告)号：US06714463B2
公开(公告)日：2004-03-30
申请号：US10251739
申请日：2002-09-20
申请人： Gong-Heum Han , Choong-Keun Kwak , Kyeong-Yoon Bae
发明人： Gong-Heum Han , Choong-Keun Kwak , Kyeong-Yoon Bae
IPC分类号： G11C700
CPC分类号： G11C8/18 , G11C7/22 , G11C8/12 , G11C2207/2281
摘要： A semiconductor memory device is provided to generate a series of pulse signals in response to the activation of an internal chip select signal from an internal chip select buffer when an external chip select signal transitions from an inactive state to an active state. With this configuration, a chip select output time (tco) is more reduced as compared to prior arts. Further, the chip select output time is reduced to be equal to an address access time (tAA) because a designer can control the chip select output time. As a result, the whole access time of the semiconductor memory device can be reduced.
摘要翻译：半导体存储器件被提供以当外部芯片选择信号从非活动状态转换到激活状态时，响应于来自内部芯片选择缓冲器的内部芯片选择信号的激活而产生一系列脉冲信号。利用这种配置，与现有技术相比，芯片选择输出时间（tco）更多地减少。此外，芯片选择输出时间减小到等于地址访问时间（tAA），因为设计者可以控制芯片选择输出时间。结果，可以减少半导体存储器件的整个访问时间。

49. 发明授权

US5576999A Redundancy circuit of a semiconductor memory device 失效
标题翻译：半导体存储器件的冗余电路
公开(公告)号：US5576999A
公开(公告)日：1996-11-19
申请号：US491348
申请日：1995-06-30
申请人： Jae-Chul Kim , Choong-Keun Kwak
发明人： Jae-Chul Kim , Choong-Keun Kwak
IPC分类号： G11C29/00 , G11C29/48 , G11C7/00
CPC分类号： G11C29/785 , G11C29/48
摘要： A redundancy circuit of the semiconductor memory device having a normal memory cell array for storing data, a redundant memory cell for repairing the fail cells in the normal memory, cell array, a normal decoder for receiving addresses and designating the normal memory cell, a redundancy decoder for selecting the redundant memory cell. The circuit includes a control part which is controlled by a control clock and has fuses for programming fail addresses of the addresses, to be applied, a transmission part which is controlled by an output signal of the control part and has a first path for outputting addresses in-phase with the addresses and a second path for outputting addresses out of phase with the addresses, thereby selecting the first path before repair to select both the normal memory cell and redundant memory cell by the normal and redundancy decoders, and cutting off the fuses corresponding to the fail addresses and selecting the second path during the repair to select the redundant memory cell by the redundancy decoder, thus enabling burn-in of both the normal memory cell and redundant memory cell during the burn-in test.
摘要翻译：具有用于存储数据的正常存储单元阵列的半导体存储器件的冗余电路，用于修复正常存储器中的故障单元的冗余存储单元，单元阵列，用于接收地址和指定正常存储单元的正常解码器，冗余用于选择冗余存储器单元的解码器。电路包括由控制时钟控制的控制部分，并且具有用于编程要应用的地址的失败地址的熔丝，由控制部分的输出信号控制的发送部分，并且具有用于输出地址的第一路径与地址同相，以及用于输出地址与地址异相的第二路径，从而在修复之前选择第一路径以通过正常和冗余解码器选择正常存储器单元和冗余存储器单元，并且切断熔丝对应于故障地址并且在修复期间选择第二路径以通过冗余解码器选择冗余存储器单元，从而在老化测试期间能够老化正常存储器单元和冗余存储器单元。

50. 发明申请

US20080080240A1 Memory devices and memory systems having the same 有权
标题翻译：具有相同的存储器件和存储器系统
公开(公告)号：US20080080240A1
公开(公告)日：2008-04-03
申请号：US11902424
申请日：2007-09-21
申请人： Kwang-Jin Lee , Won-Seok Lee , Choong-Keun Kwak
发明人： Kwang-Jin Lee , Won-Seok Lee , Choong-Keun Kwak
IPC分类号： G11C16/00
CPC分类号： H01L27/10802 , G11C7/00 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/1084 , G11C11/4063 , H01L21/84 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A non volatile memory device and a memory system having the same are disclosed. The non volatile memory device may include a memory cell array having a plurality of non volatile memory cells, a DRAM interface for exchanging data, a command and an address with an external device, a controller for selecting one of the memory cells in response to the address and performing a control operation for one of outputting data of the selected memory cell to the external device in response to the command and storing data received from the external device, and a DRAM buffer memory. The DRAM buffer memory has dynamic memory cells, and each of the dynamic memory cells has one transistor with a floating body.
摘要翻译：公开了一种非易失性存储器件和具有该非易失性存储器件的存储器系统。非易失性存储器件可以包括具有多个非易失性存储器单元的存储器单元阵列，用于交换数据的DRAM接口，与外部设备的命令和地址，用于响应于所述存储器单元选择所述存储器单元中的一个的控制器对所述存储器单元的数据的输出响应于所述命令并存储从所述外部设备接收的数据以及DRAM缓冲存储器，对所述存储单元的数据进行输出的地址和执行控制操作。 DRAM缓冲存储器具有动态存储单元，并且每个动态存储单元具有一个具有浮体的晶体管。

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