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41. 发明授权

US07184131B2 Multifunction rangefinder 有权
标题翻译：多功能测距仪
公开(公告)号：US07184131B2
公开(公告)日：2007-02-27
申请号：US10912358
申请日：2004-08-05
申请人： Peng-Fei Song , Chih-Wei Hung , Pi-Yao Chien , Kuo-Hua Yang
发明人： Peng-Fei Song , Chih-Wei Hung , Pi-Yao Chien , Kuo-Hua Yang
IPC分类号： G01C3/08
CPC分类号： G01C15/002 , G01C3/06 , G01S17/023 , G01S17/10
摘要： A multifunction rangefinder capable of measuring distance, compass location and altitude. A distance measurement unit capable of long and short distance measurements transmits a light beam to a target, receives a reflected light from the target and outputs a distance measurement signal. A compass measurement unit measures terrestrial magnetism and outputs a compass measurement signal. An altitude measurement unit measures atmospheric pressure to generate an altitude measurement signal. A microprocessor calculates a distance between the target and the multifunction rangefinder, altitude and the compass location of the target according to the distance, altitude and compass measurement signals respectively.
摘要翻译：能够测量距离，罗盘位置和高度的多功能测距仪。能够进行长距离和短距离测量的距离测量单元将光束发射到目标，接收来自目标的反射光并输出距离测量信号。罗盘测量单元测量地磁并输出罗盘测量信号。高度测量单元测量大气压力以产生高度测量信号。微处理器根据距离，高度和罗盘测量信号分别计算目标和多功能测距仪之间的距离，高度和目标的罗盘位置。

42. 发明授权

US06988319B2 Level-measuring circuit of a laser tilt meter 失效
标题翻译：激光倾斜仪的电平测量电路
公开(公告)号：US06988319B2
公开(公告)日：2006-01-24
申请号：US10865157
申请日：2004-06-10
申请人： Chih-Wei Hung
发明人： Chih-Wei Hung
IPC分类号： G01C9/06 , G01C15/00
CPC分类号： G01C9/06 , G01C9/20 , G01C2009/068 , G01C2009/182
摘要： A signal sampling circuit of a tilt sensor, suitable to be used in a tilt sensor, is described. The signal sampling circuit has a signal-generating module, a sample and hold module, and a differential module. The signal-generating module regularly generates a plurality of level-measuring signals at equally timed intervals and unidirectionally and alternately sends them to the first input pin and the second input pin of the tilt sensor, respectively. Then, the tilt sensor sequentially outputs the corresponding first and second output signals. The sample and hold module alternately samples and holds the first and the second output signals and outputs the first and the second sampling signals, respectively. The differential module receives and differentiates the first and the second sampling signals and outputs a level-estimating-result signal to a micro-controller unit to derive the tilt information of one direction.
摘要翻译：描述适用于倾斜传感器的倾斜传感器的信号采样电路。信号采样电路具有信号产生模块，采样保持模块和差分模块。信号发生模块以相同的时间间隔定期产生多个电平测量信号，并且单向地并且交替地将它们发送到倾斜传感器的第一输入引脚和第二输入引脚。然后，倾斜传感器依次输出对应的第一和第二输出信号。采样和保持模块交替采样并保持第一和第二输出信号，并分别输出第一和第二采样信号。差分模块接收并区分第一和第二采样信号，并将电平估计结果信号输出到微控制器单元以导出一个方向的倾斜信息。

43. 发明申请

US20050088641A1 Testing method for rangefinders 审中-公开
标题翻译：测距仪的测试方法
公开(公告)号：US20050088641A1
公开(公告)日：2005-04-28
申请号：US10865883
申请日：2004-06-14
申请人： Chih-Wei Hung , Peng-Fei Song , Pi-Yao Chien
发明人： Chih-Wei Hung , Peng-Fei Song , Pi-Yao Chien
IPC分类号： G01C3/08 , G01M11/00 , G01S7/497
CPC分类号： G01S7/497
摘要： A testing method for rangefinders is described and saves developing time of a required rangefinder. The method sets a default parameter of a rangefinder for emitting pulses, emits the firing pulses toward a target using an emission module according to the parameter, receives reflected pulses from the target and straylight according to the parameter by an receiving module; generates S/N data of the received pulse and the straylight with a testing system, resets the parameter or changing some components with different feature if no target signal can be recognized from the S/N data and repeats steps 2 to 4 until a target signal is recognized from the S/N data; and configures the rangefinder with the default parameter or the substitute component with which the target signal can be recognized from the S/N data.
摘要翻译：描述了测距仪的测试方法，并节省了所需测距仪的开发时间。该方法设置用于发射脉冲的测距仪的默认参数，根据参数使用发射模块向目标发射发射脉冲，根据接收模块的参数从目标和杂散光接收反射脉冲; 使用测试系统生成接收到的脉冲和杂散光的S / N数据，如果没有目标信号可以从S / N数据中识别出来，则复位参数或改变具有不同特征的部分，并重复步骤2至4，直到目标信号从S / N数据中识别; 并使用默认参数或可从S / N数据识别目标信号的替代组件来配置测距仪。

44. 发明授权

US08300462B2 Single-transistor EEPROM array and operation methods 有权
标题翻译：单晶体管EEPROM阵列及其操作方法
公开(公告)号：US08300462B2
公开(公告)日：2012-10-30
申请号：US13367122
申请日：2012-02-06
申请人： Chun-Pei Wu , Chia-Ta Shieh , Chih-Wei Hung , Mars Chen
发明人： Chun-Pei Wu , Chia-Ta Shieh , Chih-Wei Hung , Mars Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/0433 , H01L27/11565 , H01L27/11568
摘要： A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage.
摘要翻译：一种方法包括对电可擦除可编程只读存储器（EEPROM）阵列执行操作。从程序操作和擦除操作中选择操作。 EEPROM阵列包括排列成行和列的EEPROM单元，以及沿列方向延伸的多个字线。多个字线中的每一个连接到同一列中的EEPROM单元的控制栅极。 EEPROM阵列还包括沿行方向延伸的多个源极线。多个源极线中的每一个连接到同一行中的EEPROM单元的源极。在操作期间，多个源极线中的第一源极线被施加第一源极线电压，并且多个源极线中的第二源极线施加与第二源极线不同的第二源极线电压第一源线电压。

45. 发明申请

US20120134209A1 Single-Transistor EEPROM Array and Operation Methods 有权
标题翻译：单晶体管EEPROM阵列和操作方法
公开(公告)号：US20120134209A1
公开(公告)日：2012-05-31
申请号：US13367122
申请日：2012-02-06
申请人： Chun-Pei Wu , Chia-Ta Shieh , Chih-Wei Hung , Mars Chen
发明人： Chun-Pei Wu , Chia-Ta Shieh , Chih-Wei Hung , Mars Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/0433 , H01L27/11565 , H01L27/11568
摘要： A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage.
摘要翻译：一种方法包括对电可擦除可编程只读存储器（EEPROM）阵列执行操作。从程序操作和擦除操作中选择操作。 EEPROM阵列包括排列成行和列的EEPROM单元，以及沿列方向延伸的多个字线。多个字线中的每一个连接到同一列中的EEPROM单元的控制栅极。 EEPROM阵列还包括沿行方向延伸的多个源极线。多个源极线中的每一个连接到同一行中的EEPROM单元的源极。在操作期间，多个源极线中的第一源极线被施加第一源极线电压，并且多个源极线中的第二源极线施加与第二源极线不同的第二源极线电压第一源线电压。

46. 发明授权

US07518912B2 Multi-level non-volatile memory 有权
标题翻译：多级非易失性存储器
公开(公告)号：US07518912B2
公开(公告)日：2009-04-14
申请号：US11467169
申请日：2006-08-25
申请人： Chih-Wei Hung , Chih-Chen Chou
发明人： Chih-Wei Hung , Chih-Chen Chou
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A multi-level non-volatile memory including a memory cell disposed on a substrate is provided. The memory cell includes a control gate, a charge storage layer, a doped region, a select gate, and an assist gate. The control gate is disposed on the substrate. The charge storage layer is disposed between the control gate and the substrate. The doped region is disposed in the substrate at the first side of the control gate. The select gate is disposed on the sidewall of the first side of the control gate and on the substrate between the control gate and the doped region. The assist gate is disposed on the sidewall of the second side of the control gate. An inversion layer is formed in the substrate below the assist gate when a voltage is applied to the assist gate.
摘要翻译：提供了包括设置在基板上的存储单元的多级非易失性存储器。存储单元包括控制栅极，电荷存储层，掺杂区域，选择栅极和辅助栅极。控制栅极设置在基板上。电荷存储层设置在控制栅极和衬底之间。掺杂区域设置在控制栅极的第一侧的衬底中。选择栅极设置在控制栅极的第一侧的侧壁上，并且在控制栅极和掺杂区域之间的衬底上。辅助门设置在控制门的第二侧的侧壁上。当向辅助门施加电压时，在辅助栅极下方的基板中形成反型层。

47. 发明申请

US20090010533A1 METHOD AND APPARATUS FOR DISPLAYING AN ENCODED IMAGE 审中-公开
标题翻译：用于显示编码图像的方法和装置
公开(公告)号：US20090010533A1
公开(公告)日：2009-01-08
申请号：US11871244
申请日：2007-10-12
申请人： Chih-Wei Hung
发明人： Chih-Wei Hung
IPC分类号： G06T9/00
CPC分类号： H04N19/423 , H04N19/182 , H04N19/186 , H04N19/44 , H04N19/46
摘要： An apparatus for displaying an encoded image is disclosed. The apparatus comprises a display device and a decoding unit. The decoding unit acquires a Bit-Per-Pixel (BPP) value from an encoded image, acquires a bit stream from the encoded image, acquires multiple pixel data indices by segmenting the bit stream every lengths of the BPP value, acquires a pixel color value of each pixel data index by retrieving a palette comprising multiple unique pixel color values respectively labeled by the pixel data indices, and outputs the acquired pixel color values to the display device for display of the encoded image.
摘要翻译：公开了一种用于显示编码图像的装置。该装置包括显示装置和解码单元。解码单元从编码图像获取比特比特值（BPP），从编码图像获取比特流，通过分割每个BPP值的长度的比特流来获取多个像素数据索引，获取像素颜色值通过检索包括分别由像素数据索引标记的多个唯一像素颜色值的调色板，并将所获取的像素颜色值输出到显示设备以显示编码图像，从而获得每个像素数据索引。

48. 发明授权

US06855599B2 Fabrication method of a flash memory device 有权
标题翻译：闪存设备的制造方法
公开(公告)号：US06855599B2
公开(公告)日：2005-02-15
申请号：US10707668
申请日：2003-12-31
申请人： Chih-Wei Hung , Da Sung , Chih-Ming Chen
发明人： Chih-Wei Hung , Da Sung , Chih-Ming Chen
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A flash memory device includes a substrate having a trench, a deep N-type well region in the substrate, a stacked gate structure on the substrate, a first and a second spacer on a sidewall of the stacked gate, wherein the first spacer is connected with the top of the trench, a source region in the substrate under the first spacer, a drain region in the substrate under the second spacer, a P-type well region between the stacked gate and the deep N-type well region, wherein the junction between the two well regions is higher than the bottom of the trench, a doped region along the bottom and the sidewall of the trench, wherein this doped region is connected with the source region and isolates the P-type well region from the contact formed in the trench, the contact being electrically connected to the source region.
摘要翻译：闪速存储器件包括具有沟槽的衬底，衬底中的深N型阱区，衬底上的堆叠栅极结构，层叠栅极的侧壁上的第一和第二间隔物，其中第一间隔物连接在沟槽的顶部，在第一间隔物下面的衬底中的源极区域，在第二间隔物下方的衬底中的漏极区域，堆叠栅极和深N型阱区域之间的P型阱区域，其中两个阱区之间的接合点高于沟槽的底部，沿着沟槽的底部和侧壁的掺杂区域，其中该掺杂区域与源极区域连接并且将P型阱区域与形成的接触部分离开在沟槽中，触点电连接到源极区域。

49. 发明授权

US06791136B1 Memory device structure and method of fabricating the same 有权
标题翻译：存储器件结构及其制造方法
公开(公告)号：US06791136B1
公开(公告)日：2004-09-14
申请号：US10604366
申请日：2003-07-15
申请人： Hann-Jye Hsu , Chih-Wei Hung
发明人： Hann-Jye Hsu , Chih-Wei Hung
IPC分类号： H01L27108
CPC分类号： H01L27/11568 , H01L27/1052 , H01L27/115
摘要： A method of fabricating a memory device structure, where the method includes the steps of forming a tunnel oxide layer, a silicon nitride layer and a silicon oxide layer. A conductive layer is then formed on top of the silicon oxide. The conductive layer is then patterned to form a conductive gate layer. The silicon oxide layer is patterned during the same step of patterning the conductive layer, exposing the silicon nitride layer. Following that, a blanket dielectric layer is then formed on the substrate. This blanket dielectric layer is patterned with one etch step to form a spacer wall at the sides of the conductive gate layer.
摘要翻译：一种制造存储器件结构的方法，其中该方法包括形成隧道氧化物层，氮化硅层和氧化硅层的步骤。然后在氧化硅的顶部上形成导电层。然后将导电层图案化以形成导电栅极层。在图案化导电层的同一步骤中，氧化硅层被图案化，暴露氮化硅层。之后，在衬底上形成覆盖层的介电层。通过一个蚀刻步骤对该覆盖电介质层进行构图，以在导电栅极层的侧面形成间隔壁。

50. 发明授权

US08120956B2 Single-transistor EEPROM array and operation methods 有权
标题翻译：单晶体管EEPROM阵列及其操作方法
公开(公告)号：US08120956B2
公开(公告)日：2012-02-21
申请号：US12708725
申请日：2010-02-19
申请人： Chun-Pei Wu , Chia-Ta Shieh , Chih-Wei Hung , Mars Chen
发明人： Chun-Pei Wu , Chia-Ta Shieh , Chih-Wei Hung , Mars Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/0433 , H01L27/11565 , H01L27/11568
摘要： An integrated circuit structure includes an electrically erasable programmable read-only memory (EEPROM) array, which includes EEPROM cells arranged as rows and columns; a plurality of word-lines and a plurality of drain-lines extending in a column direction, and a plurality of source-lines extending in a row direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. Each of the plurality of drain-lines is connected to drains of the EEPROM cells in a same column, wherein none of the plurality of drain-lines are shared by neighboring columns of the EEPROM cells. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row.
摘要翻译：集成电路结构包括电可擦除可编程只读存储器（EEPROM）阵列，其包括排列成行和列的EEPROM单元; 沿列方向延伸的多条字线和多条漏极线以及沿行方向延伸的多条源极线。多个字线中的每一个连接到同一列中的EEPROM单元的控制栅极。多个漏极线中的每一个连接到同一列中的EEPROM单元的漏极，其中多个漏极线都不被EEPROM单元的相邻列共享。多个源极线中的每一个连接到同一行中的EEPROM单元的源极。

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