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41. 发明授权

US09105634B2 Voids in interconnect structures and methods for forming the same 有权
标题翻译：互连结构中的空隙及其形成方法
公开(公告)号：US09105634B2
公开(公告)日：2015-08-11
申请号：US13539121
申请日：2012-06-29
申请人： Jiun-Jie Huang , Ling-Sung Wang
发明人： Jiun-Jie Huang , Ling-Sung Wang
IPC分类号： H01L21/4763 , H01L23/522 , H01L23/532 , H01L21/768 , H01L49/02
CPC分类号： H01L23/5222 , H01L21/31116 , H01L21/31144 , H01L21/7682 , H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5329 , H01L23/53295 , H01L28/10 , H01L28/20 , H01L28/40 , H01L28/88 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： A device includes a dielectric layer, a passive device including a portion in the dielectric layer, and a plurality of voids in the dielectric layer and encircling the passive device.
摘要翻译：一种器件包括电介质层，包括电介质层中的一部分的无源器件，以及介电层中的多个空隙并且环绕无源器件。

42. 发明申请

US20140001597A1 Voids in Interconnect Structures and Methods for Forming the Same 有权
标题翻译：互连结构中的空隙及其形成方法
公开(公告)号：US20140001597A1
公开(公告)日：2014-01-02
申请号：US13539121
申请日：2012-06-29
申请人： Jiun-Jie Huang , Ling-Sung Wang
发明人： Jiun-Jie Huang , Ling-Sung Wang
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L23/5222 , H01L21/31116 , H01L21/31144 , H01L21/7682 , H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5329 , H01L23/53295 , H01L28/10 , H01L28/20 , H01L28/40 , H01L28/88 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： A device includes a dielectric layer, a passive device including a portion in the dielectric layer, and a plurality of voids in the dielectric layer and encircling the passive device.
摘要翻译：一种器件包括电介质层，包括电介质层中的一部分的无源器件，以及介电层中的多个空隙并且环绕无源器件。

43. 发明申请

US20130240502A1 RAPID THERMAL ANNEAL SYSTEM AND PROCESS 审中-公开
标题翻译：快速热神经系统和过程
公开(公告)号：US20130240502A1
公开(公告)日：2013-09-19
申请号：US13419946
申请日：2012-03-14
申请人： Ren-Yi CHEN , Ling-Sung Wang , Cheng-Chieh Chiang
发明人： Ren-Yi CHEN , Ling-Sung Wang , Cheng-Chieh Chiang
IPC分类号： B23K13/08
CPC分类号： H01L21/67248 , H01L21/2686 , H01L21/67115
摘要： A rapid thermal anneal system and method for processing a semiconductor substrate. The system includes a chamber configured for holding a semiconductor substrate, a heating lamp array, and a process controller operably connected to the lamp array for controlling a heating cycle of the substrate. The lamp array includes a plurality of lamps positioned to heat the substrate. The controller is operable to energize or de-energize each lamp on an individual basis, and further to simultaneously energize one or more localized groups or clusters of lamps each having at least two adjacent lamps arranged for heating geographically localized regions of the substrate having special heating needs. The system is further operable to energize all lamps in the array simultaneously. The system and method provides the capability to perform customized substrate annealing.
摘要翻译：一种用于处理半导体衬底的快速热退火系统和方法。该系统包括配置用于保持半导体衬底的腔室，加热灯阵列和可操作地连接到灯阵列的过程控制器，用于控制衬底的加热循环。灯阵列包括多个定位成加热衬底的灯。控制器可操作以在各个基础上激励或断电每个灯，并且进一步同时激励一个或多个局部化的灯组或每组具有至少两个相邻的灯的灯组，所述至少两个相邻灯被布置用于加热具有特殊加热的衬底的地理定位区域需要。该系统还可操作以同时激励阵列中的所有灯。该系统和方法提供了执行定制衬底退火的能力。

44. 发明授权

US08527915B2 Method and system for modifying doped region design layout during mask preparation to tune device performance 有权
标题翻译：在掩模准备期间修改掺杂区域设计布局以调整器件性能的方法和系统
公开(公告)号：US08527915B2
公开(公告)日：2013-09-03
申请号：US13286410
申请日：2011-11-01
申请人： Mei-Hsuan Lin , Ling-Sung Wang , Chih-Hsun Lin , Chih-Kang Chao
发明人： Mei-Hsuan Lin , Ling-Sung Wang , Chih-Hsun Lin , Chih-Kang Chao
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L21/26586 , H01L29/6659
摘要： The present disclosure provides a method and system for modifying a doped region design layout during mask preparation to tune device performance. An exemplary method includes receiving an integrated circuit design layout designed to define an integrated circuit, wherein the integrated circuit design layout includes a doped feature layout; identifying an area of the integrated circuit for device performance modification, and modifying a portion of the doped feature layout that corresponds with the identified area of the integrated circuit during a mask preparation process, thereby providing a modified doped feature layout.
摘要翻译：本公开提供了一种用于在掩模准备期间修改掺杂区域设计布局以调谐设备性能的方法和系统。一种示例性方法包括接收设计成定义集成电路的集成电路设计布局，其中集成电路设计布局包括掺杂特征布局; 识别用于器件性能修改的集成电路的区域，以及在掩模准备过程期间修改与所识别的集成电路的区域相对应的掺杂特征布局的一部分，从而提供修改的掺杂特征布局。

45. 发明授权

US08476629B2 Enhanced wafer test line structure 有权
标题翻译：增强晶圆测试线结构
公开(公告)号：US08476629B2
公开(公告)日：2013-07-02
申请号：US13246536
申请日：2011-09-27
申请人： Jiun-Jie Huang , Chi-Yen Lin , Ling-Sung Wang
发明人： Jiun-Jie Huang , Chi-Yen Lin , Ling-Sung Wang
IPC分类号： H01L29/788 , H01L27/12
CPC分类号： H01L22/34
摘要： A semiconductor wafer has a die area and a scribe area. A first dummy pad is formed in a first test line area of the scribe area and filled with a first material as part of a first metal layer. A first interlayer dielectric is formed over the first metal layer. A first interconnect pattern is formed in the die area and above the first interlayer dielectric, and a first trench pattern is formed in the first test line area of the scribe area and above the interlayer dielectric. The first interconnect pattern and the first trench pattern are filled with a second metal layer, and the first trench pattern is aligned above the first dummy pad. An enhanced test line structure including the first trench pattern and the first dummy pad is formed and probed in a back end of line (BEOL) process.
摘要翻译：半导体晶片具有模具区域和划线区域。第一虚拟焊盘形成在划线区域的第一测试线区域中，并且填充有作为第一金属层的一部分的第一材料。在第一金属层上形成第一层间电介质。第一互连图案形成在管芯区域中并且在第一层间电介质上方，并且第一沟槽图案形成在划线区域的第一测试线区域中以及层间电介质之上。第一互连图案和第一沟槽图案填充有第二金属层，并且第一沟槽图案在第一虚拟衬垫上方对准。包括第一沟槽图案和第一虚拟垫的增强的测试线结构在线后端（BEOL）工艺中被形成和探测。

46. 发明授权

US08470660B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08470660B2
公开(公告)日：2013-06-25
申请号：US13234296
申请日：2011-09-16
申请人： Mei-Hsuan Lin , Chih-Kang Chao , Chih-Hsun Lin , Ling-Sung Wang
发明人： Mei-Hsuan Lin , Chih-Kang Chao , Chih-Hsun Lin , Ling-Sung Wang
IPC分类号： H01L21/8238
CPC分类号： H01L21/8238 , H01L21/762 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/66636 , H01L29/7848
摘要： A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate.
摘要翻译：公开了制造半导体器件的方法。该示例性方法包括提供具有源极区和漏极区的衬底。该方法还包括在源极区域内的衬底中形成第一凹槽，以及在漏极区域内的衬底中形成第二凹部。第一凹部具有第一多个表面，第二凹部具有第二多个表面。该方法还包括在第一和第二凹陷中外延生长半导体材料，然后在衬底中形成浅隔离（STI）特征。

47. 发明申请

US20130093047A1 Metal-Oxide-Metal Capacitor Structure 有权
标题翻译：金属 - 氧化物 - 金属电容器结构
公开(公告)号：US20130093047A1
公开(公告)日：2013-04-18
申请号：US13274122
申请日：2011-10-14
申请人： Jiun-Jie Huang , Ling-Sung Wang , Chi-Yen Lin
发明人： Jiun-Jie Huang , Ling-Sung Wang , Chi-Yen Lin
IPC分类号： H01L29/02
CPC分类号： H01L23/5223 , H01L23/585 , H01L28/60 , H01L28/86 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A guard ring is employed to enclose the metal-oxide-metal capacitor so as to prevent moisture from penetrating into the low k dielectric material.
摘要翻译：金属氧化物 - 金属电容器包括第一电极，第二电极，多个第一指状物和多个第二指状物。每个第一指状物及其相应的第二指状物平行并由低k电介质材料隔开。采用保护环包围金属氧化物 - 金属电容器，以防止水分渗透到低k电介质材料中。

48. 发明申请

US20130075725A1 ENHANCED WAFER TEST LINE STRUCTURE 有权
标题翻译：增强型测试线结构
公开(公告)号：US20130075725A1
公开(公告)日：2013-03-28
申请号：US13246536
申请日：2011-09-27
申请人： Jiun-Jie Huang , Chi-Yen Lin , Ling-Sung Wang
发明人： Jiun-Jie Huang , Chi-Yen Lin , Ling-Sung Wang
IPC分类号： H01L23/52 , H01L21/66
CPC分类号： H01L22/34
摘要： A semiconductor wafer has a die area and a scribe area. A first dummy pad is formed in a first test line area of the scribe area and filled with a first material as part of a first metal layer. A first interlayer dielectric is formed over the first metal layer. A first interconnect pattern is formed in the die area and above the first interlayer dielectric, and a first trench pattern is formed in the first test line area of the scribe area and above the interlayer dielectric. The first interconnect pattern and the first trench pattern are filled with a second metal layer, and the first trench pattern is aligned above the first dummy pad. An enhanced test line structure including the first trench pattern and the first dummy pad is formed and probed in a back end of line (BEOL) process.
摘要翻译：半导体晶片具有模具区域和划线区域。第一虚拟焊盘形成在划线区域的第一测试线区域中，并且填充有作为第一金属层的一部分的第一材料。在第一金属层上形成第一层间电介质。第一互连图案形成在管芯区域中并且在第一层间电介质上方，并且第一沟槽图案形成在划线区域的第一测试线区域中以及层间电介质之上。第一互连图案和第一沟槽图案填充有第二金属层，并且第一沟槽图案在第一虚拟衬垫上方对准。包括第一沟槽图案和第一虚拟垫的增强的测试线结构在线后端（BEOL）工艺中被形成和探测。

49. 发明申请

US20130071995A1 Method of Manufacturing a Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130071995A1
公开(公告)日：2013-03-21
申请号：US13234296
申请日：2011-09-16
申请人： Mei-Hsuan Lin , Chih-Kang Chao , Chih-Hsun Lin , Ling-Sung Wang
发明人： Mei-Hsuan Lin , Chih-Kang Chao , Chih-Hsun Lin , Ling-Sung Wang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/8238 , H01L21/762 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/66636 , H01L29/7848
摘要： A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate.
摘要翻译：公开了制造半导体器件的方法。该示例性方法包括提供具有源极区和漏极区的衬底。该方法还包括在源极区域内的衬底中形成第一凹槽，以及在漏极区域内的衬底中形成第二凹部。第一凹部具有第一多个表面，第二凹部具有第二多个表面。该方法还包括在第一和第二凹陷中外延生长半导体材料，然后在衬底中形成浅隔离（STI）特征。

50. 发明申请

US20130049781A1 Semiconductor Devices with Self-heating Structures, Methods of Manufacture Thereof, and Testing Methods 有权
标题翻译：具有自热结构的半导体器件，其制造方法和测试方法
公开(公告)号：US20130049781A1
公开(公告)日：2013-02-28
申请号：US13221594
申请日：2011-08-30
申请人： Jia Yang Ko , Ying-Han Chiou , Ling-Sung Wang
发明人： Jia Yang Ko , Ying-Han Chiou , Ling-Sung Wang
IPC分类号： G01R31/10 , H01L21/768 , G06F19/00 , H01L23/522
CPC分类号： H01L23/345 , G01R31/2875 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices with self-heating structures, methods of manufacture thereof, and testing methods are disclosed. In one embodiment, a semiconductor device includes a workpiece, an active electrical structure disposed over the workpiece, and at least one self-heating structure disposed proximate the active electrical structure.
摘要翻译：公开了具有自热结构的半导体器件，其制造方法和测试方法。在一个实施例中，半导体器件包括工件，设置在工件上方的有源电气结构以及靠近有源电气结构设置的至少一个自热结构。

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