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41. 发明授权

US07449785B2 Solder bump on a semiconductor substrate 有权
标题翻译：半导体衬底上的焊点
公开(公告)号：US07449785B2
公开(公告)日：2008-11-11
申请号：US11347378
申请日：2006-02-06
申请人： Shin-Puu Jeng , Hao-Yi Tsai , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai
发明人： Shin-Puu Jeng , Hao-Yi Tsai , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/12 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05082 , H01L2224/05558 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2224/05552
摘要： A solder bump on a semiconductor substrate is provided. The solder bump comprises a semiconductor substrate having a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad, wherein the inorganic passivation layer has a thinner portion adjacent a top portion of the first opening. The solder bump further comprises a soft passivation layer on the inorganic passivation layer with a second opening larger than the first opening, an under bump metal layer conformally formed along the first opening and the second opening and a solder bump formed on the under bump metal layer.
摘要翻译：提供半导体衬底上的焊料凸块。焊料凸块包括其上具有顶部铜焊盘的半导体衬底，半导体衬底上的保护层和覆盖保护层的至少一个无机钝化层，第一开口露出顶部铜焊盘，其中无机钝化层具有较薄的邻近第一开口的顶部的部分。所述焊料凸块还包括在所述无机钝化层上的软钝化层，其具有大于所述第一开口的第二开口，沿所述第一开口和所述第二开口共形形成的凸块下金属层和形成在所述下凸块金属层上的焊料凸块。

42. 发明申请

US20070182007A1 Solder bump on a semiconductor substrate 有权
标题翻译：半导体衬底上的焊点
公开(公告)号：US20070182007A1
公开(公告)日：2007-08-09
申请号：US11347378
申请日：2006-02-06
申请人： Shin-Puu Jeng , Hao-Yi Tsai , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai
发明人： Shin-Puu Jeng , Hao-Yi Tsai , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/12 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05082 , H01L2224/05558 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2224/05552
摘要： A solder bump on a semiconductor substrate is provided. The solder bump comprises a semiconductor substrate having a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad, wherein the inorganic passivation layer has a thinner portion adjacent a top portion of the first opening. The solder bump further comprises a soft passivation layer on the inorganic passivation layer with a second opening larger than the first opening, an under bump metal layer conformally formed along the first opening and the second opening and a solder bump formed on the under bump metal layer.
摘要翻译：提供半导体衬底上的焊料凸块。焊料凸块包括其上具有顶部铜焊盘的半导体衬底，半导体衬底上的保护层和覆盖保护层的至少一个无机钝化层，第一开口露出顶部铜焊盘，其中无机钝化层具有较薄的邻近第一开口的顶部的部分。所述焊料凸块还包括在所述无机钝化层上的软钝化层，其具有大于所述第一开口的第二开口，沿所述第一开口和所述第二开口共形形成的凸块下金属层和形成在所述下凸块金属层上的焊料凸块。

43. 发明申请

US20070015365A1 Method and apparatus for enhanced CMP planarization using surrounded dummy design 有权
公开(公告)号：US20070015365A1
公开(公告)日：2007-01-18
申请号：US11181433
申请日：2005-07-14
申请人： Hsien-Wei Chen , Hao-Yi Tsai , Hsueh-Chung Chen , Shin-Puu Jeng , Jian-Hong Lin , Chih-Tao Lin , Shih-Hsun Hsu
发明人： Hsien-Wei Chen , Hao-Yi Tsai , Hsueh-Chung Chen , Shin-Puu Jeng , Jian-Hong Lin , Chih-Tao Lin , Shih-Hsun Hsu
IPC分类号： H01L21/461
CPC分类号： H01L21/3212 , H01L21/31053
摘要： In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.

44. 发明授权

US08749020B2 Metal e-fuse structure design 有权
标题翻译：金属电熔丝结构设计
公开(公告)号：US08749020B2
公开(公告)日：2014-06-10
申请号：US11716206
申请日：2007-03-09
申请人： Hsien-Wei Chen , Hao-Yi Tsai , Shin-Puu Jeng , Shih-Hsun Hsu
发明人： Hsien-Wei Chen , Hao-Yi Tsai , Shin-Puu Jeng , Shih-Hsun Hsu
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metal fuse in the dielectric layer; a dummy pattern adjacent the metal fuse; and a metal line in the dielectric layer, wherein a thickness of the metal fuse is substantially less than a thickness of the metal line.
摘要翻译：提供集成电路结构。集成电路结构包括半导体衬底; 半导体衬底上的电介质层; 电介质层中的金属保险丝; 与金属保险丝相邻的虚拟图案; 以及介电层中的金属线，其中金属熔丝的厚度基本上小于金属线的厚度。

45. 发明授权

US08618673B2 Package structures 有权
标题翻译：包装结构
公开(公告)号：US08618673B2
公开(公告)日：2013-12-31
申请号：US13539775
申请日：2012-07-02
申请人： Benson Liu , Hsien-Wei Chen , Shin-Puu Jeng , Hao-Yi Tsai
发明人： Benson Liu , Hsien-Wei Chen , Shin-Puu Jeng , Hao-Yi Tsai
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L25/0657 , H01L2224/16225 , H01L2224/48227 , H01L2225/06555 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die.
摘要翻译：封装结构包括衬底，第一管芯和至少一个第二管芯。衬底包括第一对平行边缘和第二对平行边缘。第一个模具安装在基板上。第一管芯包括第三对平行边缘和第四对平行边缘，其中第三对平行边缘和第四对平行边缘不平行于第一对平行边缘和第二对平行边缘，分别。至少一个第二管芯安装在第一管芯上。

46. 发明授权

US08581423B2 Double solid metal pad with reduced area 有权
标题翻译：双面实心金属垫，面积减小
公开(公告)号：US08581423B2
公开(公告)日：2013-11-12
申请号：US12272501
申请日：2008-11-17
申请人： Hsien-Wei Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng , Ying-Ju Chen
发明人： Hsien-Wei Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng , Ying-Ju Chen
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L24/03 , H01L23/3192 , H01L23/585 , H01L24/05 , H01L24/08 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/02126 , H01L2224/02166 , H01L2224/04042 , H01L2224/05009 , H01L2224/05093 , H01L2224/05094 , H01L2224/05095 , H01L2224/05552 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48684 , H01L2224/48724 , H01L2224/48739 , H01L2224/48747 , H01L2224/48755 , H01L2224/48784 , H01L2224/85 , H01L2224/85205 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/351 , H01L2924/00 , H01L2224/48744
摘要： An integrated circuit structure includes a bond pad; an Mtop pad located directly underlying the bond pad; an Mtop-1 pad having at least a portion directly underlying the Mtop pad, wherein at least one of the Mtop pad and the Mtop-1 pad has a horizontal dimension smaller than a horizontal dimension of the bond pad; a plurality of vias interconnecting the Mtop pad and the Mtop-1 pad; and a bond ball on the bond pad. Each of the Mtop pad and the Mtop-1 pad has positive enclosures to the bond ball in all horizontal directions.
摘要翻译：集成电路结构包括接合焊盘; 直接位于接合垫下面的Mtop垫; Mtop-1垫具有直接位于Mtop垫下方的至少一部分，其中Mtop垫和Mtop-1垫中的至少一个具有小于接合垫的水平尺寸的水平尺寸; 将Mtop焊盘和Mtop-1焊盘互连的多个通孔; 和粘结垫上的粘结球。每个Mtop垫和Mtop-1垫在所有水平方向上都具有粘结球的正面外壳。

47. 发明申请

US20120211902A1 BOND PAD STRUCTURE 有权
标题翻译： BOND PAD结构
公开(公告)号：US20120211902A1
公开(公告)日：2012-08-23
申请号：US13463433
申请日：2012-05-03
申请人： Shin-Puu Jeng , Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen
发明人： Shin-Puu Jeng , Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen
IPC分类号： H01L23/485 , H01L23/49
CPC分类号： H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/0401 , H01L2224/05093 , H01L2224/05096 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05552 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/16 , H01L2224/85201 , H01L2224/85205 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01049 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01087 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/30105 , H01L2924/3011 , H01L2924/37001 , H01L2924/00012 , H01L2924/00
摘要： A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive structure. In an embodiment, the contiguous conductive structure is a solid layer of conductive material. In other embodiments, the contiguous conductive structure is a conductive network including, for example, a matrix configuration or a plurality of conductive stripes. At least one dielectric spacer may interpose the conductive network. Conductive plugs may interconnect a bond pad and one of the conductive layers.
摘要翻译：提供了一种焊盘结构，其包括两个导电层和插入两个导电层的连接层。连接层包括连续的导电结构。在一个实施例中，邻接的导电结构是导电材料的固体层。在其它实施例中，连续导电结构是包括例如矩阵配置或多个导电条纹的导电网络。至少一个电介质间隔物可以插入导电网络。导电插头可以将接合焊盘和导电层中的一个互连。

48. 发明授权

US08203209B2 Bond pad design for reducing the effect of package stress 有权
标题翻译：焊盘设计，减少封装应力的影响
公开(公告)号：US08203209B2
公开(公告)日：2012-06-19
申请号：US12813763
申请日：2010-06-11
申请人： Chen-Hua Yu , Shin-Puu Jeng , Hao-Yi Tsai , Hsien-Wei Chen
发明人： Chen-Hua Yu , Shin-Puu Jeng , Hao-Yi Tsai , Hsien-Wei Chen
IPC分类号： H01L23/498
CPC分类号： H01L24/11 , H01L23/3192 , H01L2224/0401 , H01L2224/05006 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/05552 , H01L2224/05572 , H01L2224/05655 , H01L2224/13006 , H01L2224/13099 , H01L2224/16225 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/3511 , H01L2924/00012 , H01L2924/00014 , H01L2924/013
摘要： An integrated circuit structure includes a semiconductor substrate, and an active device formed at a front surface of the semiconductor substrate. A bond pad is over the front surface of the semiconductor substrate. The bond pad has a first dimension in a first direction parallel to the front surface of the semiconductor substrate. A bump ball is over the bond pad, wherein the bump ball has a diameter in the first direction, and wherein an enclosure of the first dimension and the diameter is greater than about −1 μm.
摘要翻译：集成电路结构包括半导体衬底和形成在半导体衬底的前表面的有源器件。接合焊盘在半导体衬底的前表面之上。接合焊盘在与半导体基板的前表面平行的第一方向上具有第一尺寸。凸块球在接合垫上方，其中凸块球具有在第一方向上的直径，并且其中第一尺寸和直径的外壳大于约-1μm。

49. 发明申请

US20110287627A1 SEMICONDUCTOR TEST PAD STRUCTURES 有权
公开(公告)号：US20110287627A1
公开(公告)日：2011-11-24
申请号：US13197003
申请日：2011-08-03
申请人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
IPC分类号： H01L21/768
CPC分类号： H01L22/34 , H01L24/05 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.
摘要翻译：具有集成的模具隔离保护屏障的半导体测试焊盘互连结构。互连结构包括多个堆叠的金属层，每个层具有通过介电材料层与其它测试焊盘分离的导电测试焊盘。在一个实施例中，至少一个金属通孔条被嵌入到互连结构中，并将金属层中的每个测试焊盘电连接在一起。在一些实施例中，通孔棒基本上沿着由每个测试垫限定的整个第一侧面延伸。在其它实施例中，可以提供一对相对的通孔条，其布置在限定在半导体晶片上的划线带中的模切单切锯切线的相对侧上。

50. 发明授权

US08013333B2 Semiconductor test pad structures 有权
标题翻译：半导体测试板结构
公开(公告)号：US08013333B2
公开(公告)日：2011-09-06
申请号：US12267021
申请日：2008-11-07
申请人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , H01L24/05 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.
摘要翻译：具有集成的模具隔离保护屏障的半导体测试焊盘互连结构。互连结构包括多个堆叠的金属层，每个层具有通过介电材料层与其它测试焊盘分离的导电测试焊盘。在一个实施例中，至少一个金属通孔条被嵌入到互连结构中，并将金属层中的每个测试焊盘电连接在一起。在一些实施例中，通孔棒基本上沿着由每个测试垫限定的整个第一侧面延伸。在其他实施例中，可以提供一对相对的通孔条，其布置在限定在半导体晶片上的划线带中的模切单切锯切线的相对侧上。

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