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41. 发明申请

US20070049736A1 INTERFERON-LIKE PROTEIN ZCYTO21 审中-公开
公开(公告)号：US20070049736A1
公开(公告)日：2007-03-01
申请号：US11548138
申请日：2006-10-10
申请人： Paul Sheppard , Scott Presnell , Brian Fox , Teresa Gilbert , Betty Haldeman , Francis Grant
发明人： Paul Sheppard , Scott Presnell , Brian Fox , Teresa Gilbert , Betty Haldeman , Francis Grant
IPC分类号： C07K16/24
CPC分类号： C07K14/47 , C07K14/52 , C07K2319/00
摘要： The present invention relates to polynucleotide and polypeptide molecules for Zcyto21, an interferon-like protein, which is most closely related to interferon-α at the amino acid sequence level. The present invention also includes antibodies to the Zcyto21 polypeptides, and methods of using the polynucleotides and polypeptides.

42. 发明申请

US20060263851A1 SOLUBLE INTERLEUKIN-20 RECEPTOR 有权
公开(公告)号：US20060263851A1
公开(公告)日：2006-11-23
申请号：US11458367
申请日：2006-07-18
申请人： Donald Foster , Wenfeng Xu , Karen Madden , James Kelly , Cindy Sprecher , Cameron Brandt , Mark Rixon , Scott Presnell , Brian Fox
发明人： Donald Foster , Wenfeng Xu , Karen Madden , James Kelly , Cindy Sprecher , Cameron Brandt , Mark Rixon , Scott Presnell , Brian Fox
IPC分类号： C12P21/06 , C07K14/715
CPC分类号： C07K16/2866 , A61K38/00 , C07K14/7155 , C07K2319/00
摘要： A soluble receptor to IL-20 having two polypeptide subunits, IL-20RA (formerly called ZcytoR7) and IL-20RB (formerly called DIRS1). The two subunits are preferably linked together. In one embodiment one subunit is fused to the constant region of the light chain of an immunoglobulin, and the other subunit is fused to the constant region of the heavy chain of the immunoglobulin. The light chain and the heavy chain are connected via a disulfide bond.

43. 发明授权

US07117416B1 Method and apparatus to facilitate self-testing of a system on chip 有权
标题翻译：促进片上系统自检的方法和装置
公开(公告)号：US07117416B1
公开(公告)日：2006-10-03
申请号：US11021636
申请日：2004-12-23
申请人： Brian Fox
发明人： Brian Fox
IPC分类号： G01R31/28
CPC分类号： G01R31/318516
摘要： A method and apparatus for providing a system-on-a-chip comprising a processor and a configurable system logic (CSL) including a plurality of banks arranged in an array coupled to the processor. The system on a chip further includes a built-in self test (BIST) mechanism coupled to the CSL to perform tests on the CSL to verify that the banks and interconnections between the banks are functioning properly.
摘要翻译：一种用于提供片上系统的方法和装置，包括处理器和可配置系统逻辑（CSL），可配置系统逻辑（CSL）包括布置在耦合到处理器的阵列中的多个存储体。芯片上的系统还包括耦合到CSL的内置自检（BIST）机制，以对CSL进行测试，以验证银行之间的银行和互连是否正常工作。

44. 发明申请

US20060165030A1 Method of and system for transmitting a mobile agent for instruction execution 审中-公开
标题翻译：用于发送用于指令执行的移动代理的方法和系统
公开(公告)号：US20060165030A1
公开(公告)日：2006-07-27
申请号：US11006287
申请日：2004-12-07
申请人： Brian Fox , Jonathan Lei
发明人： Brian Fox , Jonathan Lei
IPC分类号： H04Q7/00
CPC分类号： H04L67/306 , G06F9/4862 , H04W4/16 , H04W80/00
摘要： A method of executing programmable instructions includes receiving at a device a mobile agent from a mobile agent dispatching device. The mobile agent includes a state of a virtual machine. The method also includes executing at the device one or more instructions identified by the mobile agent, thereby changing the state of the virtual machine.
摘要翻译：执行可编程指令的方法包括在设备处从移动代理调度设备接收移动代理。移动代理包括虚拟机的状态。该方法还包括在设备处执行由移动代理标识的一个或多个指令，从而改变虚拟机的状态。

45. 发明申请

US20060123396A1 Method of and instruction set for executing operations on a device 失效
标题翻译：在设备上执行操作的方法和指令集
公开(公告)号：US20060123396A1
公开(公告)日：2006-06-08
申请号：US11006286
申请日：2004-12-07
申请人： Brian Fox , Jonathan Lei
发明人： Brian Fox , Jonathan Lei
IPC分类号： G06F9/44
CPC分类号： G06F9/45504
摘要： A method for executing operations on a device includes executing one or more bytecode language instructions associated with a mobile agent. The mobile agent includes a state of a virtual machine and the bytecode language includes instructions such WARP, MESG; ESEL, ALERT, BROWSE, CAPS, SLEEP, and GPS.
摘要翻译：用于在设备上执行操作的方法包括执行与移动代理相关联的一个或多个字节代码语言指令。移动代理包括虚拟机的状态，并且字节码语言包括诸如WARP，MESG之类的指令; ESEL，ALERT，BROWSE，CAPS，SLEEP和GPS。

46. 发明申请

US20050267035A1 Peptide and polypeptide inhibitors of complement C1s 审中-公开
标题翻译：肽和多肽补体C1s抑制剂
公开(公告)号：US20050267035A1
公开(公告)日：2005-12-01
申请号：US11156843
申请日：2005-06-20
申请人： Robert West , Paul Sheppard , Brian Fox
发明人： Robert West , Paul Sheppard , Brian Fox
IPC分类号： A61K38/00 , A61P29/00 , A61P31/00 , C07K14/435 , C07K14/815 , A61K38/10 , A61K38/08 , C07K7/06 , C07K7/08
CPC分类号： C07K14/815 , A61K38/00 , C07K14/43536
摘要： The complement system plays an important role in providing resistance to infections and in the pathogenesis of tissue injury. Yet an inappropriate activation of complement can result in a variety of disorders. The present invention provides C1s catalytic site-directed moieties, C1s exosite binding moieties, and bivalent polypeptide inhibitors comprising such moieties, which can be used to treat conditions characterized by inappropriate complement activation.
摘要翻译：补体系统在提供抗感染和组织损伤的发病机制中起重要作用。然而补体的不适当活化可导致多种疾病。本发明提供C1s催化位点定向部分，C1s外部结合部分和包含这些部分的二价多肽抑制剂，其可用于治疗以不适当的补体活化为特征的病症。

47. 发明授权

US06870397B1 Input/output circuit with user programmable functions 有权
标题翻译：具有用户可编程功能的输入/输出电路
公开(公告)号：US06870397B1
公开(公告)日：2005-03-22
申请号：US10635992
申请日：2003-08-06
申请人： Brian Fox , Andreas Papaliolios , Steven P. Winegarden , Edmond Y. Cheung
发明人： Brian Fox , Andreas Papaliolios , Steven P. Winegarden , Edmond Y. Cheung
IPC分类号： H03K19/177 , H03K19/77
CPC分类号： H03K19/17744
摘要： The I/O circuit of the present invention provides optimal flexibility and performance using a number of different structures and methods. The present invention provides a signal follower circuit for an input pad. In one embodiment, the output buffer is capable of injecting a constant onto a pad during reconfiguration of a configurable system logic circuit. The present invention also provides a circuit for generating a programmable data propagation delay, thereby guaranteeing zero hold time for an arbitrary input register. Zero hold time is accomplished by allowing the user to optimally characterize clock delay to a given input/output circuit. The present invention also provides fast switching between input pads, thereby minimizing data propagation delay between the input pads. Additionally, the present invention reduces time spent in production product test by facilitating the testing of multiple routes with one test configuration. A circuit expanding the number of data input channels available to system routing is provided. Lastly, a plurality of identical input/output block tiles (IOBTs) is disclosed, thereby enabling each I/O circuit to provide the same signals regardless of the IOBTs location in the I/O circuit.
摘要翻译：本发明的I / O电路使用多种不同的结构和方法提供最佳的灵活性和性能。本发明提供一种用于输入焊盘的信号跟随器电路。在一个实施例中，输出缓冲器能够在配置的系统逻辑电路的重新配置期间将常数注入焊盘。本发明还提供了一种用于产生可编程数据传播延迟的电路，由此保证任意输入寄存器的零保持时间。零保持时间通过允许用户最佳地表征给定输入/输出电路的时钟延迟来实现。本发明还提供了输入焊盘之间的快速切换，从而使输入焊盘之间的数据传播延迟最小化。此外，本发明通过促进对具有一个测试配置的多个路由的测试来减少在生产产品测试中花费的时间。提供了扩展系统路由可用数据输入通道数量的电路。最后，公开了多个相同的输入/输出块块（IOBT），从而使每个I / O电路能够提供相同的信号，而不管I / O电路中的IOBT位置如何。

48. 发明授权

US06857092B1 Method and apparatus to facilitate self-testing of a system on a chip 有权
标题翻译：促进芯片上系统自检的方法和装置
公开(公告)号：US06857092B1
公开(公告)日：2005-02-15
申请号：US09866080
申请日：2001-05-25
申请人： Brian Fox
发明人： Brian Fox
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318516
摘要： A method and apparatus for providing a system-on-a-chip comprising a processor and a configurable system logic (CSL) including a plurality of banks arranged in an array coupled to the processor. The system on a chip further includes a built-in self test (BIST) mechanism coupled to the CSL to perform tests on the CSL to verify that the banks and interconnections between the banks are functioning properly.
摘要翻译：一种用于提供片上系统的方法和装置，包括处理器和可配置系统逻辑（CSL），可配置系统逻辑（CSL）包括布置在耦合到处理器的阵列中的多个存储体。芯片上的系统还包括耦合到CSL的内置自检（BIST）机制，以对CSL进行测试，以验证银行之间的银行和互连是否正常工作。

49. 发明授权

US06851047B1 Configuration in a configurable system on a chip 有权
标题翻译：配置在芯片上的可配置系统中
公开(公告)号：US06851047B1
公开(公告)日：2005-02-01
申请号：US09419386
申请日：1999-10-15
申请人： Brian Fox , Andreas Papaliolios
发明人： Brian Fox , Andreas Papaliolios
IPC分类号： G06F13/14 , G06F13/28 , G06F15/177 , H03K19/177
CPC分类号： G06F13/14
摘要： The present invention allows a user to customize the configuration sequence of a configurable system on a chip (CSoC), thereby adding considerable flexibility to the configuration process. The present invention also provides certain features, transparent to the user, which optimize system resources and ensure the correct initialization of the CSoC. The CSoC leverages an on-chip central processing unit (CPU) to control the configuration process of the configurable system logic (CSL). Advantageously, the CSL configuration memory cells as well as other programmable locations in the CSoC are addressable as part of a system bus address space. The system bus is a multi-use structure that can be used for both configuring and reading of memory cells. In this manner, the CSoC optimizes system resources.
摘要翻译：本发明允许用户定制芯片（CSoC）上可配置系统的配置顺序，从而为配置过程增加了相当大的灵活性。本发明还提供对用户透明的某些特征，其优化系统资源并确保CSoC的正确初始化。 CSoC利用片上中央处理单元（CPU）来控制可配置系统逻辑（CSL）的配置过程。有利地，CSL配置存储器单元以及CSoC中的其他可编程位置作为系统总线地址空间的一部分可寻址。系统总线是一种多用途结构，可用于配置和读取存储单元。以这种方式，CSoC优化系统资源。

50. 发明授权

US4822084A Sliding door lock assembly 失效
标题翻译：滑动门锁组件
公开(公告)号：US4822084A
公开(公告)日：1989-04-18
申请号：US39956
申请日：1987-04-20
申请人： Brian Fox
发明人： Brian Fox
IPC分类号： E05B65/08 , E05C21/02
CPC分类号： E05B65/0888 , Y10S292/46 , Y10T292/293 , Y10T292/45
摘要： A door lock assembly of the type for use with sliding doors, windows or the like for securing a moveable member relative to a stationary member, the assembly including an elongated bar member adapted to be attached at one end to a support frame mounting the moveable and stationary members and having at its opposite end a selectively operable latch mechanism adapted to coact with the moveable member so as to selectively lock and unlock such moveable member relative to the stationary member.
摘要翻译：一种用于与滑动门，窗户等一起用于固定可移动构件相对于固定构件的类型的门锁组件，该组件包括细长杆构件，其适于在一端附接到支撑框架，该支撑框架安装可移动和固定构件并且在其相对端具有适于与可移动构件共同作用的选择性操作的闩锁机构，以便相对于固定构件选择性地锁定和解锁该可移动构件。

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