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41. 发明授权

US07355922B2 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM 有权
公开(公告)号：US07355922B2
公开(公告)日：2008-04-08
申请号：US11429856
申请日：2006-05-08
申请人： James Brian Johnson , Brent Keeth , Feng (Dan) Lin
发明人： James Brian Johnson , Brent Keeth , Feng (Dan) Lin
IPC分类号： G11C8/00 , H03L7/06
CPC分类号： G11C11/4076 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C2207/2254 , H03L7/0812 , H03L7/095
摘要： A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock. The input of the start signal to a second counter is delayed to delay the initiation of a running count of the control clock pulses. The delay, which may be expressed as an integer number of clock cycles, may be equal to an input/output delay of the memory device. The method may be modified by inputting the start signal to an offset counter before initiating the production of the running count of the read clock pulses in the first counter. The offset counter may be loaded with a value equal to a programmed latency less a synchronization overhead. Once the running counts are initiated, each time a read command is received, a then current value of the running count of control clock pulses from the second counter is latched or held. The held value is compared to the running count of read clock pulses from the first counter, with the read clock signal being used to output data in response to the comparison. Apparatus for implementing the disclosed methods are also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

42. 发明申请

US20080037342A1 APPARATUS AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY 有权
标题翻译：用于修复半导体存储器的装置和方法
公开(公告)号：US20080037342A1
公开(公告)日：2008-02-14
申请号：US11876477
申请日：2007-10-22
申请人： Chris Martin , Troy Manning , Brent Keeth
发明人： Chris Martin , Troy Manning , Brent Keeth
IPC分类号： G11C7/00 , G11C17/18
CPC分类号： G11C17/165 , G11C29/4401 , G11C29/789 , G11C29/802 , G11C29/808 , G11C2029/4402
摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.
摘要翻译：用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。当第一存储器访问对应于第一缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。

43. 发明申请

US20070153595A1 Apparatus and method for repairing a semiconductor memory 有权
公开(公告)号：US20070153595A1
公开(公告)日：2007-07-05
申请号：US11714979
申请日：2007-03-07
申请人： Chris Martin , Troy Manning , Brent Keeth
发明人： Chris Martin , Troy Manning , Brent Keeth
IPC分类号： G11C29/00
CPC分类号： G11C17/165 , G11C29/4401 , G11C29/789 , G11C29/802 , G11C29/808 , G11C2029/4402
摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

44. 发明申请

US20070152743A1 256 Meg dynamic random access memory 审中-公开
公开(公告)号：US20070152743A1
公开(公告)日：2007-07-05
申请号：US11715112
申请日：2007-03-07
申请人： Brent Keeth , Layne Bunker , Raymond Beffa , Frank Ross
发明人： Brent Keeth , Layne Bunker , Raymond Beffa , Frank Ross
IPC分类号： G05F1/10
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

45. 发明授权

US07155561B2 Method and system for using dynamic random access memory as cache memory 有权
标题翻译：使用动态随机存取存储器作为高速缓冲存储器的方法和系统
公开(公告)号：US07155561B2
公开(公告)日：2006-12-26
申请号：US11230836
申请日：2005-09-19
申请人： Brent Keeth , Brian M. Shirley , Charles H. Dennison
发明人： Brent Keeth , Brian M. Shirley , Charles H. Dennison
IPC分类号： G06F12/16
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0897 , G11C7/1006 , G11C7/1042 , G11C11/406 , G11C11/409 , G11C15/043
摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
摘要翻译：高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且还包括2个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

46. 发明申请

US20060265565A1 Dual edge command 有权
公开(公告)号：US20060265565A1
公开(公告)日：2006-11-23
申请号：US11495418
申请日：2006-07-28
申请人： Joo Choi , Troy Manning , Brent Keeth
发明人： Joo Choi , Troy Manning , Brent Keeth
IPC分类号： G06F13/00
CPC分类号： G11C11/4076 , G06F12/0207 , G06F13/1668 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C11/408 , G11C11/409
摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

47. 发明申请

US20060045206A1 Method and system for generating reference voltages for signal receivers 有权
公开(公告)号：US20060045206A1
公开(公告)日：2006-03-02
申请号：US10930543
申请日：2004-08-30
申请人： Brent Keeth , Joo Choi , George Pax , Ronnie Harrison , David Ovard , Dragos Dimitriu , Troy Manning , Roy Greeff , Greg King , Brian Johnson
发明人： Brent Keeth , Joo Choi , George Pax , Ronnie Harrison , David Ovard , Dragos Dimitriu , Troy Manning , Roy Greeff , Greg King , Brian Johnson
IPC分类号： H04L27/06
CPC分类号： H04L25/062
摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

48. 发明申请

US20060044891A1 Memory system and method for strobing data, command and address signals 有权
公开(公告)号：US20060044891A1
公开(公告)日：2006-03-02
申请号：US10931472
申请日：2004-08-31
申请人： Feng Lin , Brent Keeth , Brian Johnson , Seong-hoon Lee
发明人： Feng Lin , Brent Keeth , Brian Johnson , Seong-hoon Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222
摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

49. 发明申请

US20060028905A1 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM 有权
公开(公告)号：US20060028905A1
公开(公告)日：2006-02-09
申请号：US10910838
申请日：2004-08-04
申请人： James Johnson , Brent Keeth , Feng (Dan) Lin
发明人： James Johnson , Brent Keeth , Feng (Dan) Lin
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C2207/2254 , H03L7/0812 , H03L7/095
摘要： A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock. The input of the start signal to a second counter is delayed to delay the initiation of a running count of the control clock pulses. The delay, which may be expressed as an integer number of clock cycles, may be equal to an input/output delay of the memory device. The method may be modified by inputting the start signal to an offset counter before initiating the production of the running count of the read clock pulses in the first counter. The offset counter may be loaded with a value equal to a programmed latency less a synchronization overhead. Once the running counts are initiated, each time a read command is received, a then current value of the running count of control clock pulses from the second counter is latched or held. The held value is compared to the running count of read clock pulses from the first counter, with the read clock signal being used to output data in response to the comparison. Apparatus for implementing the disclosed methods are also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

50. 发明授权

US06948027B2 Method and system for using dynamic random access memory as cache memory 失效
公开(公告)号：US06948027B2
公开(公告)日：2005-09-20
申请号：US10815877
申请日：2004-03-30
申请人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
发明人： Brent Keeth , Brian M. Shirley , Charles H. Dennison , Kevin J. Ryan
IPC分类号： G11C7/10 , G11C11/406 , G11C11/409 , G11C15/04 , G06F12/00
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0897 , G11C7/1006 , G11C7/1042 , G11C11/406 , G11C11/409 , G11C15/043
摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

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