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41. 发明授权

US08176374B2 Data register control of TDI/AX1 to the data register 有权
标题翻译：数据寄存器控制TDI / AX1
公开(公告)号：US08176374B2
公开(公告)日：2012-05-08
申请号：US13039517
申请日：2011-03-03
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/318558 , G01R31/2851 , G01R31/3177 , G01R31/318536 , G01R31/318572 , G01R31/318594
摘要： The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.
摘要翻译：本公开描述了用于直接访问存在于许多串行连接的JTAG Tap域的扫描路径中的JTAG Tap域的新颖的方法和装置。由JTAG控制器直接扫描访问所选的Tap域，可以使用与Tap域关联并连接到JTAG控制器的辅助数字或模拟终端。在直接扫描访问期间，辅助数字或模拟端子用作所选Tap域和JTAG控制器之间的串行数据输入和串行数据输出路径。

42. 发明授权

US08171361B2 Multiplexer Control Circuitry for TAP Domain Selection Circuitry 有权
标题翻译： TAP域选择电路的多路复用器控制电路
公开(公告)号：US08171361B2
公开(公告)日：2012-05-01
申请号：US13157955
申请日：2011-06-10
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/28 , G01R31/318555 , G01R31/318572
摘要： Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.
摘要翻译：今天，许多IEEE 1149.1 Tap域的实例都包含在集成电路（IC）中。虽然所有TAP域可以在可在IC外部访问的扫描路径上串行连接，但通常优选具有访问Tap域或Tap域的选择性。因此，点选区域选择电路可能包含在IC中，并与Tap域一起放置在扫描路径中。理想情况下，如果需要修改在扫描路径中选择了哪个Tap域，则Tap域选择电路应该仅存在于扫描路径中。本公开描述了一种新颖的方法和装置，其允许在其已经用于选择分组域之后从扫描路径移除分接区域选择电路，并且当需要选择不同的分接区域时，将其替换回扫描路径。

43. 发明授权

US08168970B2 Die having embedded circuitry with test and test enable circuitry 有权
标题翻译：具有嵌入式电路的测试和测试使能电路
公开(公告)号：US08168970B2
公开(公告)日：2012-05-01
申请号：US13097352
申请日：2011-04-29
申请人： Lee D. Whetsel , Richard L. Antley
发明人： Lee D. Whetsel , Richard L. Antley
IPC分类号： H01L23/58
CPC分类号： G01R31/2886 , G01R1/0491 , H01L22/32 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.
摘要翻译：晶片上的晶片的及时测试降低了制造IC的成本。本公开描述了通过在模具的顶表面上添加测试焊盘来减少测试时间的模具测试结构和过程。添加的测试垫允许测试仪同时探测和测试模具中的更多电路。此外，添加的测试垫有助于减少访问和测试管芯内的电路所需的测试接线开销的量，从而减小管芯尺寸。

44. 发明授权

US08156394B2 Selectively accessing test access ports in a multiple test access port environment 有权
公开(公告)号：US08156394B2
公开(公告)日：2012-04-10
申请号：US13098799
申请日：2011-05-02
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318536 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318572
摘要： A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

45. 发明授权

US08145962B2 TAP interface select circuit with TMS/RCK or RCK lead 有权
标题翻译： TAP接口选择电路与TMS / RCK或RCK引线
公开(公告)号：US08145962B2
公开(公告)日：2012-03-27
申请号：US13102742
申请日：2011-05-06
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/31722 , G01R31/31723 , G01R31/31727 , G01R31/318541 , G01R31/318558
摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.
摘要翻译：本公开描述了可以在集成电路中的集成电路或嵌入式核心上使用的减少的引脚总线。总线可用于串行访问电路，其中IC或引脚上的引脚的可用性受限制。总线可用于各种串行通信操作，例如但不限于IC或核心设计的串行通信相关测试，仿真，调试和/或跟踪操作。本公开的其他方面包括使用减少的针脚总线用于仿真，调试和跟踪操作以及功能操作。在本公开的第五方面中，一种接口选择电路，图41-49提供了选择性地使用图5的5信号接口。 41或图3的3信号接口。 8。

46. 发明授权

US08136002B2 Communication between controller and addressed target devices over data signal 有权
标题翻译：通过数据信号在控制器和寻址的目标器件之间进行通信
公开(公告)号：US08136002B2
公开(公告)日：2012-03-13
申请号：US12970148
申请日：2010-12-16
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G06F7/02
CPC分类号： G01R31/31723 , G01R31/31722 , G01R31/31725 , G01R31/31727 , G01R31/3177 , G01R31/318572 , G06F11/261 , G06F11/267 , G06F11/27 , G06F11/3466
摘要： An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin. After being enabled, the Trace domain acquires data from a functioning circuit within the IC in response to a first clock and outputs the acquired data from the IC in response to a second clock. An addressable two pin interface loads and updates instructions and data to a TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation. Trace circuitry within an IC can operate autonomously to store and output functional data occurring in the IC. The store and output operations of the trace circuitry are transparent to the functional operation of the IC. An auto-addressing RAM memory stores input data at an input address generated in response to an input clock, and outputs stored data from an output address generated in response to an output clock.
摘要翻译：可寻址接口选择性地启用IC内的JTAG TAP域操作或跟踪域操作。启用后，TAP从单个数据引脚接收TMS和TDI输入。在启用之后，响应于第一时钟，跟踪域从IC内的功能电路获取数据，并且响应于第二时钟从IC输出所获取的数据。可寻址的两针接口将指令和数据加载并更新到IC内的TAP域。多个IC中的指令或数据更新操作同时发生。过程使用数据帧将数据从寻址的目标设备发送到控制器，每个数据帧包括报头位和数据位。标头位的逻辑电平用于启动，继续和停止向控制器传输数据。控制器和多个目标设备之间的数据和时钟信号接口提供每个目标设备被单独寻址并命令执行JTAG或跟踪操作。 IC内的跟踪电路可以自主操作来存储和输出在IC中发生的功能数据。跟踪电路的存储和输出操作对于IC的功能操作是透明的。自动寻址RAM存储器将输入数据存储在响应于输入时钟产生的输入地址处，并且从响应于输出时钟产生的输出地址输出存储的数据。

47. 发明授权

US08132064B2 Selectively accessing test access ports in a multiple test access port environment 有权
标题翻译：在多个测试访问端口环境中选择性访问测试访问端口
公开(公告)号：US08132064B2
公开(公告)日：2012-03-06
申请号：US13098776
申请日：2011-05-02
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318536 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318572
摘要： A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
摘要翻译： TAP链接模块（21,51）允许通过单个TAP接口（20）从测试总线（13）控制和访问多个TAP（TAP 1-4）。

48. 发明授权

US08094765B2 Clock and mode signals controlling data communication in three states 有权
标题翻译：时钟和模式信号控制三种状态下的数据通信
公开(公告)号：US08094765B2
公开(公告)日：2012-01-10
申请号：US12946439
申请日：2010-11-15
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： H04L7/00
CPC分类号： G06F13/4291 , G01R31/31725 , G01R31/31726 , G01R31/318536 , G01R31/318594 , G06F1/04 , G06F1/06 , H04B1/18 , H04J3/0644 , H04L7/0008
摘要： Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.
摘要翻译：数据通过两个单独的电路或电路组进行通信，每个电路或电路组通过顺序地反转时钟和模式输入的作用而具有时钟和模式输入。数据通信电路具有数据输入，数据输出，用于定时或同步数据输入和/或输出通信的时钟输入，以及用于控制数据输入和/或输出通信的模式输入。时钟/模式信号连接到一个电路的时钟输入和另一个电路的模式输入。模式/时钟信号连接到一个电路的模式输入和另一个电路的时钟输入。模式和时钟信号对模式/时钟和时钟/模式信号或其反相的作用选择数据通信电路中的一个或另一个。

49. 发明申请

US20110289370A1 OPTIMIZED JTAG INTERFACE 有权
公开(公告)号：US20110289370A1
公开(公告)日：2011-11-24
申请号：US13197000
申请日：2011-08-03
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/2815 , G01R31/3172 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/318541 , G01R31/318555 , G01R31/318558 , G01R31/318572 , G06F11/3656
摘要： An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

50. 发明授权

US08065578B2 Inverted TCK access port selector selecting one of plural TAPs 有权
标题翻译：反向TCK访问端口选择器选择多个TAP之一
公开(公告)号：US08065578B2
公开(公告)日：2011-11-22
申请号：US12880527
申请日：2010-09-13
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/31723 , G01R31/31725 , G01R31/31727 , G01R31/318533
摘要： The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.
摘要翻译：本公开描述了一种用于允许控制器选择和访问设备中的不同类型的接入端口的新颖方法和装置。访问端口的选择和访问仅使用设备的专用TDI，TMS，TCK和TDO信号终端来实现。当单个设备连接到控制器时，当多个设备以菊花链布置并连接到控制器时，或者当多个设备被放置在可寻址的并行布置中时，可以实现设备访问端口的选择和访问，并且连接到控制器。在本公开中还提供和描述了另外的实施例。

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