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41. 发明申请

US20050162303A1 Programming method of controlling the amount of write current applied to phase change memory device and write driver circuit therefor 有权
标题翻译：控制施加到相变存储器件的写入电流和写入驱动器电路的编程方法
公开(公告)号：US20050162303A1
公开(公告)日：2005-07-28
申请号：US11079198
申请日：2005-03-15
申请人： Baek-Hyung Cho , Woo-Yeong Cho , Hyung-Rok Oh , Byung-Gil Choi
发明人： Baek-Hyung Cho , Woo-Yeong Cho , Hyung-Rok Oh , Byung-Gil Choi
IPC分类号： G11C13/00 , G11C13/02 , G11C16/02 , H01L27/105 , H01L45/00 , H03M3/00
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0069 , G11C2013/0078
摘要： A programming method which controls the amount of a write current applied to a Phase-change Random Access Memory (PRAM), and a write driver circuit realizing the programming method. The programming method includes maintaining a ratio of a resistance of the PCM in the higher resistance state to a resistance of the PCM in the lower resistance state constant or substantially constant independent of an ambient temperature. The ratio may be maintained by increasing, decreasing, or keeping the same a reset current and/or a set current.
摘要翻译：控制施加到相变随机存取存储器（PRAM）的写入电流的量的编程方法以及实现编程方法的写入驱动器电路。编程方法包括保持PCM在较高电阻状态下的电阻与PCM在较低电阻状态下的电阻的比率恒定或基本恒定，而与环境温度无关。可以通过增加，减少或保持相同的复位电流和/或设定电流来维持该比率。

42. 发明授权

US08654595B2 Nonvolatile memory device with a clamping voltage generation circuit for compensating the variations in memory cell parameters 有权
标题翻译：具有用于补偿存储单元参数变化的钳位电压产生电路的非易失性存储器件
公开(公告)号：US08654595B2
公开(公告)日：2014-02-18
申请号：US13604688
申请日：2012-09-06
申请人： Chan-Kyung Kim , Hong-Sun Hwang , Chul-Woo Park , Sang-Beom Kang , Hyung-Rok Oh
发明人： Chan-Kyung Kim , Hong-Sun Hwang , Chul-Woo Park , Sang-Beom Kang , Hyung-Rok Oh
IPC分类号： G11C7/02
CPC分类号： G11C5/145 , G11C7/12 , G11C11/1673
摘要： A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to generate a clamping voltage responsive to a first voltage having a level based on the reference cell, and to feed back the clamping voltage to the clamping circuit.
摘要翻译：非易失性存储器件包括非易失性单元阵列，其包括存储单元和参考单元，钳位电路电连接到存储单元并且被配置为在读取操作期间钳位施加到数据感测线的电压，以及钳位电压产生单元被配置为响应于具有基于参考单元的电平的第一电压产生钳位电压，并且将钳位电压反馈到钳位电路。

43. 发明授权

US07993961B2 Layout structure in semiconductor memory device comprising global word lines, local word lines, global bit lines and local bit lines 有权
标题翻译：包括全局字线，局部字线，全局位线和局部位线的半导体存储器件中的布局结构
公开(公告)号：US07993961B2
公开(公告)日：2011-08-09
申请号：US12509617
申请日：2009-07-27
申请人： Hyung-Rok Oh , Sang-Beom Kang , Du-Eung Kim
发明人： Hyung-Rok Oh , Sang-Beom Kang , Du-Eung Kim
IPC分类号： H01L21/06
CPC分类号： G11C7/18 , G11C5/063 , G11C13/0004 , G11C2213/72 , H01L27/24
摘要： A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing all of the global word line, the local word line, the global bit line and the local bit line at conductive layers among at least three layers; at least two of the global word line, the local word line, the global bit line and the local bit line are together disposed in parallel on one conductive layer. Signal lines constituting a semiconductor memory device are disposed in a hierarchical structure, whereby a semiconductor memory device advantageously having high integration, high speed and high performance may be obtained.
摘要翻译：提供了具有层次结构的半导体存储器件中的线路布局结构和方法。在具有全局字线和本地字线以及全局位线和局部位线的半导体存储器件中，并且单独地布置全局全局字线，局部字线，全局位线和局部位在至少三层中的导电层上线; 全局字线，本地字线，全局位线和局部位线中的至少两个在一个导电层上一并设置。构成半导体存储器件的信号线以分层结构设置，从而可以获得有利地具有高集成度，高速度和高性能的半导体存储器件。

44. 发明授权

US07589367B2 Layout structure in semiconductor memory device comprising global work lines, local work lines, global bit lines and local bit lines 有权
标题翻译：包括全局工作线，本地工作线，全局位线和局部位线的半导体存储器件中的布局结构
公开(公告)号：US07589367B2
公开(公告)日：2009-09-15
申请号：US11316871
申请日：2005-12-27
申请人： Hyung-Rok Oh , Sang-Beom Kang , Du-Eung Kim
发明人： Hyung-Rok Oh , Sang-Beom Kang , Du-Eung Kim
IPC分类号： H01L27/108
CPC分类号： G11C7/18 , G11C5/063 , G11C13/0004 , G11C2213/72 , H01L27/24
摘要： A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing all of the global word line, the local word line, the global bit line and the local bit line at conductive layers among at least three layers; at least two of the global word line, the local word line, the global bit line and the local bit line are together disposed in parallel on one conductive layer. Signal lines constituting a semiconductor memory device are disposed in a hierarchical structure, whereby a semiconductor memory device advantageously having high integration, high speed and high performance may be obtained.
摘要翻译：提供了具有层次结构的半导体存储器件中的线路布局结构和方法。在具有全局字线和本地字线以及全局位线和局部位线的半导体存储器件中，并且单独地布置全局全局字线，局部字线，全局位线和局部位在至少三层中的导电层上线; 全局字线，本地字线，全局位线和局部位线中的至少两个在一个导电层上一并设置。构成半导体存储器件的信号线以分层结构设置，从而可以获得有利地具有高集成度，高速度和高性能的半导体存储器件。

45. 发明申请

US20060226459A1 Layout structure in semiconductor memory device and layout method therefor 有权
标题翻译：半导体存储器件的布局结构及其布局方法
公开(公告)号：US20060226459A1
公开(公告)日：2006-10-12
申请号：US11316871
申请日：2005-12-27
申请人： Hyung-Rok Oh , Sang-Beom Kang , Du-Eung Kim
发明人： Hyung-Rok Oh , Sang-Beom Kang , Du-Eung Kim
IPC分类号： H01L29/94
CPC分类号： G11C7/18 , G11C5/063 , G11C13/0004 , G11C2213/72 , H01L27/24
摘要： A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing all of the global word line, the local word line, the global bit line and the local bit line at conductive layers among at least three layers; at least two of the global word line, the local word line, the global bit line and the local bit line are together disposed in parallel on one conductive layer. Signal lines constituting a semiconductor memory device are disposed in a hierarchical structure, whereby a semiconductor memory device advantageously having high integration, high speed and high performance may be obtained.
摘要翻译：提供了具有层次结构的半导体存储器件中的线路布局结构和方法。在具有全局字线和本地字线以及全局位线和局部位线的半导体存储器件中，并且单独地布置全局全局字线，局部字线，全局位线和局部位在至少三层中的导电层上线; 全局字线，本地字线，全局位线和局部位线中的至少两个在一个导电层上一并设置。构成半导体存储器件的信号线以分层结构设置，从而可以获得有利地具有高集成度，高速度和高性能的半导体存储器件。

46. 发明申请

US20140169069A1 Resistive Memory Device, System Including the Same and Method of Reading Data in the Same 审中-公开
标题翻译：电阻式存储器件，包括相同的系统和读取数据的方法
公开(公告)号：US20140169069A1
公开(公告)日：2014-06-19
申请号：US14094021
申请日：2013-12-02
申请人： Hyung-Rok Oh
发明人： Hyung-Rok Oh
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/10 , G11C7/1057 , G11C7/22 , G11C11/1673 , G11C13/0002 , G11C13/0061 , G11C13/0069 , G11C13/04 , G11C2013/0071 , G11C2213/79
摘要： A resistive memory device includes a memory cell array, a memory interface and a read sensing circuit. The memory cell array includes a plurality of resistive memory cells coupled to a plurality of wordlines and a plurality of bitlines. The memory interface is configured to communicate with a memory controller. The read sensing circuit is coupled to the bitlines and includes at least one sensing node. The read sensing circuit performs a precharge operation to precharge the at least one sensing node between a first time point of receiving an active command through the memory interface and a second time point of receiving a read command through the memory interface, and senses data stored in the resistive memory cells to provide read data.
摘要翻译：电阻式存储器件包括存储单元阵列，存储器接口和读取感测电路。存储单元阵列包括耦合到多个字线和多个位线的多个电阻存储器单元。存储器接口被配置为与存储器控制器通信。读取感测电路耦合到位线并且包括至少一个感测节点。读取感测电路执行预充电操作，以在通过存储器接口接收活动命令的第一时间点和通过存储器接口接收读取命令的第二时间点之间对至少一个感测节点进行预充电，并且感测存储在电阻存储单元提供读数据。

47. 发明申请

US20100090213A1 ONE-TIME PROGRAMMABLE DEVICES INCLUDING CHALCOGENIDE MATERIAL AND ELECTRONIC SYSTEMS INCLUDING THE SAME 有权
标题翻译：一次性可编程器件，包括合成材料和包括其中的电子系统
公开(公告)号：US20100090213A1
公开(公告)日：2010-04-15
申请号：US12638599
申请日：2009-12-15
申请人： Chang-Wook Jeong , Jun-Hyok Kong , Hyung-Rok Oh
发明人： Chang-Wook Jeong , Jun-Hyok Kong , Hyung-Rok Oh
IPC分类号： H01L29/18
CPC分类号： G11C17/16 , G11C13/0004 , G11C17/165
摘要： A method of programming a one-time programmable device is provided. A switching device disposed in a substrate is turned on and a program current is applied to a fuse electrically connected to the switching device, thereby cutting the fuse. The fuse includes a first electrode electrically connected to the switching device, a second electrode spaced apart from the first electrode, and a chalcogenide pattern disposed between the first and second electrodes. Related one-time programmable devices, phase change memory devices and electronic systems are also disclosed.
摘要翻译：提供了一种编程一次性可编程器件的方法。设置在基板中的开关装置导通，并且将编程电流施加到与开关装置电连接的保险丝，从而切断保险丝。保险丝包括电连接到开关装置的第一电极，与第一电极间隔开的第二电极和设置在第一和第二电极之间的硫族化物图案。还公开了相关的一次性可编程器件，相变存储器件和电子系统。

48. 发明申请

US20080007986A1 ONE-TIME PROGRAMMABLE DEVICES INCLUDING CHALCOGENIDE MATERIAL, ELECTRONIC SYSTEMS INCLUDING THE SAME AND METHODS OF OPERATING THE SAME 有权
标题翻译：包括氯化铝材料的一次可编程器件，包括其的电子系统及其操作方法
公开(公告)号：US20080007986A1
公开(公告)日：2008-01-10
申请号：US11564751
申请日：2006-11-29
申请人： Chang-Wook Jeong , Jun-Hyok Kong , Hyung-Rok Oh
发明人： Chang-Wook Jeong , Jun-Hyok Kong , Hyung-Rok Oh
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C13/0004 , G11C17/165
摘要： A method of programming a one-time programmable device is provided. A switching device disposed in a substrate is turned on and a program current is applied to a fuse electrically connected to the switching device, thereby cutting the fuse. The fuse includes a first electrode electrically connected to the switching device, a second electrode spaced apart from the first electrode, and a chalcogenide pattern disposed between the first and second electrodes. Related one-time programmable devices, phase change memory devices and electronic systems are also disclosed.
摘要翻译：提供了一种编程一次性可编程器件的方法。设置在基板中的开关装置导通，并且将编程电流施加到与开关装置电连接的保险丝，从而切断保险丝。保险丝包括电连接到开关装置的第一电极，与第一电极间隔开的第二电极和设置在第一和第二电极之间的硫族化物图案。还公开了相关的一次性可编程器件，相变存储器件和电子系统。

49. 发明申请

US20120182786A1 BIDIRECTIONAL RESISTIVE MEMORY DEVICES USING SELECTIVE READ VOLTAGE POLARITY 失效
标题翻译：使用选择性读取电压极性的双向电阻存储器件
公开(公告)号：US20120182786A1
公开(公告)日：2012-07-19
申请号：US13349167
申请日：2012-01-12
申请人： In-Gyu Baek , Hyung-Rok Oh , Hong-Sun Hwang
发明人： In-Gyu Baek , Hyung-Rok Oh , Hong-Sun Hwang
IPC分类号： G11C11/21
CPC分类号： G11C13/004 , G11C8/10 , G11C11/16 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007
摘要： A memory device includes a memory cell array including a plurality of memory cells, each including a bidirectional variable resistance element and an input/output circuit configured to determine a polarity for a read voltage to be applied to a selected memory cell among the plurality of memory cells and to apply the read voltage with the determined polarity to the selected memory cell. The input/output circuit may include a polarity determination circuit configured to determine the polarity responsive to a determination mode signal and a driver circuit configured to apply the read voltage with the determined polarity to the selected memory cell.
摘要翻译：存储器件包括存储单元阵列，其包括多个存储器单元，每个存储器单元包括双向可变电阻元件和输入/输出电路，该输入/输出电路被配置为确定要施加到多个存储器中的选定存储单元的读取电压的极性并将所确定的极性的读取电压施加到所选存储单元。输入/输出电路可以包括极性确定电路，其被配置为响应于确定模式信号确定极性，并且驱动器电路被配置为将所确定的极性的读取电压施加到所选存储单元。

50. 发明授权

US07974115B2 One-time programmable devices including chalcogenide material and electronic systems including the same 有权
标题翻译：一次性可编程器件包括硫族化物材料和包括其的电子系统
公开(公告)号：US07974115B2
公开(公告)日：2011-07-05
申请号：US12638599
申请日：2009-12-15
申请人： Chang-Wook Jeong , Jun-Hyok Kong , Hyung-Rok Oh
发明人： Chang-Wook Jeong , Jun-Hyok Kong , Hyung-Rok Oh
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C13/0004 , G11C17/165
摘要： A switching device disposed in a substrate is turned on and a program current is applied to a fuse electrically connected to a switching device, thereby cutting the fuse. The fuse includes a first electrode electrically connected to the switching device, a second electrode spaced apart from the first electrode, and a chalcogenide pattern disposed between the first and second electrodes.
摘要翻译：设置在基板中的开关装置导通，并且将编程电流施加到与开关装置电连接的保险丝，从而切断熔丝。保险丝包括电连接到开关装置的第一电极，与第一电极间隔开的第二电极和设置在第一和第二电极之间的硫族化物图案。

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