专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US08435864B2 Process for single and multiple level metal-insulator-metal integration with a single mask 有权
标题翻译：单层和多层金属绝缘体金属与单一掩模集成的工艺
公开(公告)号：US08435864B2
公开(公告)日：2013-05-07
申请号：US13432440
申请日：2012-03-28
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/32136 , H01L28/75
摘要： A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.
摘要翻译：提供一种制造MIM电容器的方法。该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。上板被切下，使得上板的边缘位于掩模下方。使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

42. 发明申请

US20120133022A1 METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE 有权
标题翻译：无平面化和相关半导体器件制造被动元件的方法
公开(公告)号：US20120133022A1
公开(公告)日：2012-05-31
申请号：US13359634
申请日：2012-01-27
申请人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L29/92 , H01L29/8605
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

43. 发明授权

US08120143B2 Integrated circuit comb capacitor 有权
标题翻译：集成电路梳状电容
公开(公告)号：US08120143B2
公开(公告)日：2012-02-21
申请号：US12034728
申请日：2008-02-21
申请人： Daniel C. Edelstein , Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Sarah L. Lane , Anthony K. Stamper
发明人： Daniel C. Edelstein , Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Sarah L. Lane , Anthony K. Stamper
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L28/87 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.
摘要翻译：本发明涉及具有电容器电极的集成电路梳状电容器，其与在相同金属布线级别和相同间距处形成的其它互连和通孔触点相比，在相邻的电容器电极之间具有增加的电容。本发明实现了一种电容器，其使电容容限最小化并且在寄生电极 - 基板电容耦合中保持对称性，而不会通过使用至多一个附加的非临界光掩模来不利地影响在相同布线级别形成的其它互连和通孔触点。

44. 发明授权

US08093679B2 Integrated BEOL thin film resistor 有权
标题翻译：集成BEOL薄膜电阻
公开(公告)号：US08093679B2
公开(公告)日：2012-01-10
申请号：US13023579
申请日：2011-02-09
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
IPC分类号： H01L29/00 , H01L27/10 , H01L29/74 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.
摘要翻译：在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。

45. 发明授权

US08039354B2 Passive components in the back end of integrated circuits 有权
标题翻译：集成电路后端的被动元件
公开(公告)号：US08039354B2
公开(公告)日：2011-10-18
申请号：US12849086
申请日：2010-08-03
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Oliver Plouchart , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Oliver Plouchart , Anthony K. Stamper
IPC分类号： H01L21/02
CPC分类号： H01L23/5228 , H01L23/5227 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.
摘要翻译：通过使用与后端的其余部分相同的沉积工艺和材料在后端形成被动部件。电阻器通过连接在后端的第n（n + 1）等级上的串联单独结构而形成。电容器通过从后端的多个层构造一组垂直电容器板而形成，该板通过垂直连接构件在后端的两层或更多层上连接电极而形成。

46. 发明授权

US07902629B2 Integrated BEOL thin film resistor 有权
标题翻译：集成BEOL薄膜电阻
公开(公告)号：US07902629B2
公开(公告)日：2011-03-08
申请号：US12271942
申请日：2008-11-17
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , John M. Cotte , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Eric J. White
IPC分类号： H01L29/00 , H01L27/10 , H01L29/74 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.
摘要翻译：在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。

47. 发明授权

US07551421B2 Capacitor having electrode terminals at same end of capacitor to reduce parasitic inductance 失效
标题翻译：在电容器的同一端具有电极端子以减少寄生电感的电容器
公开(公告)号：US07551421B2
公开(公告)日：2009-06-23
申请号：US11616064
申请日：2006-12-26
申请人： Eric Thompson , Anil K. Chinthakindi
发明人： Eric Thompson , Anil K. Chinthakindi
IPC分类号： H01G4/228 , H01G4/005
CPC分类号： H01G4/306 , H01G4/232 , H01G4/33 , H01L23/5223 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A capacitor is disclosed having reduced impedance. In one embodiment, the capacitor includes a cathode including a first terminal and a first set of electrodes extending from the first terminal in a first layer, each electrode in the first set coupled to one corresponding electrode of a second set of electrodes in a second layer by at least one contact; and an anode including a second terminal and a third set of electrodes extending from the second terminal in the second layer, each electrode in the third set coupled to one corresponding electrode of a fourth set of electrodes in the first layer by at least one contact, wherein the first terminal and the second terminal are on a same end of the capacitor.
摘要翻译：公开了具有减小的阻抗的电容器。在一个实施例中，电容器包括阴极，其包括第一端子和从第一层中的第一端子延伸的第一组电极，第一组中的每个电极耦合到第二层中的第二组电极的一个对应电极至少有一个联系人; 以及包括从第二层中的第二端子延伸的第二端子和第三组电极的阳极，第三组中的每个电极通过至少一个触点耦合到第一层中的第四组电极的一个对应电极，其中所述第一端子和所述第二端子位于所述电容器的同一端上。

48. 发明授权

US07466534B2 High capacitance density vertical natural capacitors 失效
标题翻译：高电容密度垂直天然电容
公开(公告)号：US07466534B2
公开(公告)日：2008-12-16
申请号：US11422457
申请日：2006-06-06
申请人： Anil K. Chinthakindi
发明人： Anil K. Chinthakindi
IPC分类号： H01G4/228 , H01L27/108 , H01L29/94
CPC分类号： H01G4/228 , H01G4/30 , H01G4/33 , H01L23/5223 , H01L28/60 , H01L2924/0002 , Y10T29/417 , Y10T29/435 , H01L2924/00
摘要： Disclosed are embodiments of a capacitor with inter-digitated vertical plates and a method of forming the capacitor such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line processing by masking connecting points with nodes, by etching the dielectric material from between the vertical plates and by etching a sacrificial material from below the vertical plates. Etching of the dielectric material from between the plates forms air gaps and various techniques can be used to cause the plates to collapse in on these air gaps, once the sacrificial material is removed. Any remaining air gaps can be filled by depositing a second dielectric material (e.g., a high k dielectric), which will further increase the capacitance density and will encapsulate the capacitor in order to make the reduced distance between the vertical plates permanent.
摘要翻译：公开了具有数字化的垂直板的电容器的实施例以及形成电容器的方法，使得板之间的有效间隙距离减小。该间隙宽度减小显着增加了电容器的电容密度。通过用节点掩蔽连接点，通过从垂直板之间蚀刻电介质材料，并通过从垂直板下方蚀刻牺牲材料，在线加工的后端完成间隙宽度减小。一旦牺牲材料被去除，介质材料之间的介电材料的蚀刻形成气隙，并且可以使用各种技术来使板在这些气隙上塌陷。可以通过沉积第二电介质材料（例如，高k电介质）来填充任何剩余的空气间隙，这将进一步增加电容密度并将封装电容器，以便使垂直板之间的距离减小。

49. 发明授权

US07456463B2 Capacitor having electrodes at different depths to reduce parasitic capacitance 失效
标题翻译：电容器具有不同深度的电极以减少寄生电容
公开(公告)号：US07456463B2
公开(公告)日：2008-11-25
申请号：US11671614
申请日：2007-02-06
申请人： Eric Thompson , Anil K. Chinthakindi
发明人： Eric Thompson , Anil K. Chinthakindi
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01G4/33 , H01G4/228 , H01G4/306 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： Capacitors are disclosed having reduced parasitic capacitance. In one embodiment, the capacitor includes a first set of electrodes, each electrode of the first set extending through at least one of a plurality of back-end-of-line (BEOL) layers above a substrate; a second set of electrodes, each electrode of the second set extending through at least one of the BEOL layers, and wherein each electrode of the second set extends to a greater depth of the plurality of BEOL layers than each electrode of the first set.
摘要翻译：公开了具有降低的寄生电容的电容器。在一个实施例中，电容器包括第一组电极，第一组的每个电极延伸穿过衬底上方的多个后端行（BEOL）层中的至少一个; 第二组电极，第二组的每个电极延伸穿过至少一个BEOL层，并且其中第二组的每个电极延伸到多个BEOL层的比第一组的每个电极更大的深度。

50. 发明申请

US20080224259A1 METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20080224259A1
公开(公告)日：2008-09-18
申请号：US12106374
申请日：2008-04-21
申请人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L29/00 , H01L21/02
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式