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41. 发明授权

US06360288B1 Method and modules for control of pipelines carrying data using pipelines carrying control signals 失效
标题翻译：使用承载控制信号的管道控制承载数据的管道的方法和模块
公开(公告)号：US06360288B1
公开(公告)日：2002-03-19
申请号：US08953767
申请日：1997-10-17
申请人： Ivan E. Sutherland , William S. Coates , Charles E. Molnar , Robert F. Sproull
发明人： Ivan E. Sutherland , William S. Coates , Charles E. Molnar , Robert F. Sproull
IPC分类号： G06F1300
CPC分类号： G06F9/3869 , G06F9/3867
摘要： A computer system is described in which control of the flow of data items in one pipeline is achieved using the values of control elements in another pipeline. Typically, each pipeline includes elements known as “places” and “paths,” and the pipelines have special connections between them by which the data present in a place in a first pipeline can be used to control the disposition of data in the second pipeline. For example, the first pipeline can control the second pipeline to enable the addition, deletion, or steering of data items in the second pipeline.
摘要翻译：描述了一种计算机系统，其中使用另一流水线中的控制元件的值来实现一条流水线中的数据项流的控制。通常，每个管道包括被称为“地点”和“路径”的元件，并且管道在它们之间具有特殊的连接，通过该特殊连接，可以使用存在于第一管道中的位置的数据来控制第二管道中的数据的布置。例如，第一流水线可以控制第二流水线，以允许第二流水线中的数据项的添加，删除或转向。

42. 发明授权

US6085316A Layered counterflow pipeline processor with anticipatory control 失效
标题翻译：具有预期控制的分层逆流管线处理器
公开(公告)号：US6085316A
公开(公告)日：2000-07-04
申请号：US123587
申请日：1998-07-28
申请人： Ivan E. Sutherland , Charles E. Molnar, deceased , Ian W. Jones , William S. Coates , Jon Lexau
发明人： Ivan E. Sutherland , Charles E. Molnar, deceased , Ian W. Jones , William S. Coates , Jon Lexau
IPC分类号： G06F9/38 , G06F15/78 , G06F15/80 , G06F9/28 , G06F13/40
CPC分类号： G06F9/3873 , G06F15/8007 , G06F15/8053 , G06F9/3867
摘要： A layered counterflow pipeline structure is described in which sub-tasks performed at each stage in a counterflow pipeline processor are separated into different layers. As words flow through the counterflow pipeline processor, they are divided into partial words which are supplied to the different layers, GET, CHECK and PROCESS, for appropriate handling by that portion of each stage. In the GET layer, partial words passing through each stage are analyzed to determine whether they constitute an encounter pair. In the CHECK layer a determination is made as to whether the word selected by the GET layer requires further modification. Finally, in the PROCESS layer operations are performed on the words themselves based upon control messages from the other layers. The layers of the processor communicate with each other using suitable communication paths such as First In First Out registers.
摘要翻译：描述了分层逆流管线结构，其中在逆流管线处理器中的每个阶段执行的子任务被分成不同的层。当文字流过逆流流水线处理器时，它们被分成供应给不同层的部分单词，GET，CHECK和PROCESS，以便每个阶段的该部分进行适当的处理。在GET层中，分析通过每个阶段的部分单词，以确定它们是否构成遇到对。在CHECK层中，确定由GET层选择的单词是否需要进一步修改。最后，在PROCESS层中，基于来自其他层的控制消息对单词本身执行操作。处理器的层使用诸如先进先出寄存器之类的合适的通信路径彼此通信。

43. 发明授权

US5742182A Symmetric selector circuit for event logic 失效
标题翻译：事件逻辑对称选择器电路
公开(公告)号：US5742182A
公开(公告)日：1998-04-21
申请号：US665154
申请日：1996-06-13
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： G06F7/00 , H03K3/037 , H03K3/356 , H03K17/693 , H03K19/00
CPC分类号： H03K17/693 , H03K3/037 , H03K3/356113 , H03K3/356182
摘要： A selector circuit with symmetry is disclosed. It steers input transition events to one of two outputs according to the value of a data input signal. The selector circuit includes a first flip-flop and a second flip-flop. Depending on the state of a data input, one of the two flip-flops is enabled and the other is disabled. The disabled flip-flop will be in a tristate mode. The enabled flip-flop continues storing its data, and may load the disabled flip-flop with this data. The selector circuit further includes pass gates to couple the outputs of the flip-flops based on the state of the event input.
摘要翻译：公开了一种具有对称性的选择器电路。根据数据输入信号的值，将输入转换事件转换为两个输出之一。选择器电路包括第一触发器和第二触发器。取决于数据输入的状态，两个触发器中的一个被使能，另一个被禁用。禁用的触发器将处于三态模式。启用的触发器继续存储其数据，并且可以使用该数据加载禁用的触发器。选择器电路还包括传递门，以根据事件输入的状态耦合触发器的输出。

44. 发明授权

US5638009A Three conductor asynchronous signaling 失效
标题翻译：三导体异步信号
公开(公告)号：US5638009A
公开(公告)日：1997-06-10
申请号：US333554
申请日：1994-11-02
申请人： Ivan E. Sutherland , Charles E. Molnar
发明人： Ivan E. Sutherland , Charles E. Molnar
IPC分类号： G06F9/38 , G06F13/364 , H04L25/08 , H03K19/0185
CPC分类号： G06F9/3824 , G06F13/364 , G06F9/384 , G06F9/3842 , G06F9/3867 , G06F9/3869 , H04L25/085
摘要： A technique is described for transmitting events over three or more conductors in which a sequence of activity of the conductors for information transfer is provided. To transfer information, the conductors are placed in an active state in a sequential manner, and then returned to an inactive state after each has been active in a time period short enough to prevent all conductors from being active at the same time.
摘要翻译：描述了用于在三个或更多个导体上发送事件的技术，其中提供用于信息传送的导体的一系列活动。为了传输信息，导体以顺序的方式被置于活动状态，然后在每个已经在足够短的时间段内被激活之后恢复到非活动状态，以防止所有导体同时被激活。

45. 发明授权

US5600848A Counterflow pipeline processor with instructions flowing in a first direction and instruction results flowing in the reverse direction 失效
标题翻译：逆流管线处理器，其指令沿第一方向流动，指令结果沿相反方向流动
公开(公告)号：US5600848A
公开(公告)日：1997-02-04
申请号：US477533
申请日：1995-06-07
申请人： Robert F. Sproull , Ivan E. Sutherland
发明人： Robert F. Sproull , Ivan E. Sutherland
IPC分类号： G06F9/38 , G06F13/00
CPC分类号： G06F9/3842 , G06F9/3824 , G06F9/384 , G06F9/3867
摘要： A general purpose computer capable of executing instructions of the type commonly found in multiple-address register-oriented instruction sets such as the SPARC instruction set is built from a counterflow pipeline. Communication in the pipeline flows both ways between adjacent stages and different stages in the pipeline are able to perform different instructions. Instructions flow through the pipeline in one direction, ("up") and the answers computed by previous instructions, called "results," flow in the other direction, ("down"). Comparison circuits in each stage of the pipeline permit instructions to select and copy the data values they need from the downward flowing stream of previously computed results. The comparison circuits also remove from the downward flowing stream previously computed results that would be rendered obsolete by execution of the present instruction.
摘要翻译：能够执行通常在诸如SPARC指令集的多地址寄存器定向指令集中发现的类型的指令的通用计算机从逆流管线构建。管道中的通信在相邻阶段之间流动，管道中的不同阶段能够执行不同的指令。指令沿着一个方向流过管道（“向上”），由先前的指令计算的答案称为“结果”，沿着另一个方向（“向下”）流动。流水线的每个阶段的比较电路允许指令从先前计算结果的向下流动的流中选择和复制他们需要的数据值。比较电路还从向下流动的流中去除先前计算的结果，这些结果将通过执行本指令而过时。

46. 发明授权

US5592103A System for fast switching of time critical input signals 失效
标题翻译：用于快速切换时间关键输入信号的系统
公开(公告)号：US5592103A
公开(公告)日：1997-01-07
申请号：US499407
申请日：1995-07-03
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： G06F9/38 , G06F13/364 , H04L25/08 , H03K19/01
CPC分类号： G06F9/3824 , G06F13/364 , G06F9/384 , G06F9/3842 , G06F9/3867 , G06F9/3869 , H04L25/085
摘要： A technique is provided for switching circuitry in a manner which allows the circuit to respond quickly to changes in some critical input signals expected to arrive last. In the preferred embodiment the circuits of this invention are provided in triple logic column form. A circuit will typically include at least two logic columns, each having three portions serially coupled between a high and a low potential source. The middle portion of each logic column is connected to the output node and to receive the critical input signal expected to arrive last, or the input signal with the critical timing requirement. The upper and lower portions of each logic column are connected to receive the remaining input signals, that is those input signals not expected to be changing at the time the critical input signal is received. Thus, the state of the upper and lower portions of the logic column can be "set-up" in advance, in readiness for the critical input condition. Typically, the invention provides three logic columns - - - one logic column for causing the output to follow changes in the state of the critical input signals, one logic column for causing the output to have a state which is the reverse of the state of the critical input signals, and a final logic column for holding the condition of the output constant regardless of changes in the state of the critical input signals.
摘要翻译：提供了一种以允许电路快速响应预期到达的一些关键输入信号的变化的方式来切换电路的技术。在优选实施例中，本发明的电路以三逻辑列形式提供。电路通常将包括至少两个逻辑列，每个逻辑列具有串联耦合在高电位和低电位之间的三个部分。每个逻辑列的中间部分连接到输出节点并接收预期到达的关键输入信号，或具有临界定时要求的输入信号。每个逻辑列的上部和下部连接以接收剩余的输入信号，也就是在接收到关键输入信号时预计不会改变的那些输入信号。因此，逻辑列的上部和下部的状态可以预先“设置”，准备好处于关键输入条件。通常，本发明提供了三个逻辑列 - 一个逻辑列，用于使输出跟随关键输入信号状态的变化，一个逻辑列用于使输出具有与该状态相反的状态关键输入信号，以及用于保持输出常数条件的最终逻辑列，而不管关键输入信号的状态如何变化。

47. 发明授权

US5187800A Asynchronous pipelined data processing system 失效
标题翻译：异步流水线数据处理系统
公开(公告)号：US5187800A
公开(公告)日：1993-02-16
申请号：US107839
申请日：1987-10-13
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： G06F5/08 , G11C19/00
CPC分类号： G06F5/08 , G11C19/00
摘要： An asynchronous form of pipeline processor has a storage capability for partially processed data. When the processor is empty, it functions as a combinatorial circuit producing resultant data processed as desired. As necessary, the processor registers data, however, it continues to advance other data as rapidly as possible. A control unit individually provides binary control signals to a plurality of processing apparatus to maintain order with respect to processing and storing data. Switching structures controlled by the control unit along with amplifiers are provided at the input and output of individual processors to set the processing apparatus to process or store data. Processing several sets of data simultaneously while preserving proper order enables the system to do logic and arithmetic processing at a relatively high speed.
摘要翻译：流水线处理器的异步形式具有部分处理数据的存储能力。当处理器为空时，它用作产生根据需要处理的结果数据的组合电路。必要时，处理器注册数据，但是，它仍然尽可能快地推进其他数据。控制单元向多个处理装置分别提供二进制控制信号以维持关于处理和存储数据的顺序。在单个处理器的输入和输出处提供由控制单元控制的开关结构以及放大器，以设置处理装置来处理或存储数据。同时处理多组数据同时保持正确的顺序使系统能够以较高的速度执行逻辑和算术处理。

48. 发明授权

US07020779B1 Secure, distributed e-mail system 有权
标题翻译：安全的分布式电子邮件系统
公开(公告)号：US07020779B1
公开(公告)日：2006-03-28
申请号：US09644086
申请日：2000-08-22
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： H04K1/00 , H04L9/00
CPC分类号： H04L63/0428 , H04L63/062
摘要： An e-mail handling system, wherein e-mail messages are entered, transported and stored, comprises a central key repository, means for encrypting a message using a key associated with the message, means for adding the key to the central key repository; and means for deleting the key for a message when the message is to be made unrecallable.
摘要翻译：一种电子邮件处理系统，其中输入，传输和存储电子邮件消息，包括中央密钥存储库，用于使用与该消息相关联的密钥加密消息的装置，用于将密钥添加到中央密钥存储库的装置; 以及当消息被做成不可呼叫时，删除消息的密钥的装置。

49. 发明授权

US06559531B1 Face to face chips 有权
标题翻译：面对面的筹码
公开(公告)号：US06559531B1
公开(公告)日：2003-05-06
申请号：US09418120
申请日：1999-10-14
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： H01L2302
CPC分类号： H01L23/642 , H01L23/48 , H01L25/0652 , H01L2224/16 , H01L2225/06513 , H01L2225/06531 , H01L2924/01046 , H01L2924/01079 , H01L2924/3025
摘要： An integrated circuit device includes first and second arrays of semiconductor dice. Each array of dice is arranged in face-to-face relation to the other array of dice, thus forming a lower layer of dice and an upper layer of dice. The layers are aligned so that each upper layer die straddles two or more of the lower layer dice, thus defining overlap regions. In the overlap regions, signal pads of one layer are aligned with corresponding signal pads of the other layer. The two layers are spaced apart, thus creating a capacitance-based communication path between the upper and lower layers via the signal paths.
摘要翻译：集成电路器件包括半导体晶片的第一和第二阵列。每个骰子阵列与另一个骰子阵列面对面地布置，从而形成下层骰子和上层骰子。这些层被对准，使得每个上层模具跨越下层骰子中的两个或更多个，从而限定重叠区域。在重叠区域中，一层的信号焊盘与另一层的相应信号焊盘对准。两层间隔开，从而通过信号路径在上层和下层之间产生基于电容的连通路径。

50. 发明授权

US06486709B2 Distributing data to multiple destinations within an asynchronous circuit 有权
公开(公告)号：US06486709B2
公开(公告)日：2002-11-26
申请号：US09854094
申请日：2001-05-11
申请人： Ivan E. Sutherland , Josephus C. Ebergen
发明人： Ivan E. Sutherland , Josephus C. Ebergen
IPC分类号： H03K1920
CPC分类号： G05B19/045 , G05B2219/23289 , G05B2219/25263 , G05B2219/25306
摘要： One embodiment of the present invention provides a system that asynchronously distributes data to a plurality of destinations within a digital circuit. Upon receiving a data item to be distributed, the system monitors asynchronous control signals associated with the destinations, wherein a given asynchronous control signal indicates that a given destination is free to receive the data item. For each destination that is free to receive the data item, the system forwards the data item to the destination asynchronously without waiting for a system clock signal, and also changes an asynchronous control signal associated with the destination to indicate that the destination is not free to receive a subsequent data item.

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