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41. 发明授权

US06998334B2 Semiconductor devices with permanent polymer stencil and method for manufacturing the same 有权
公开(公告)号：US06998334B2
公开(公告)日：2006-02-14
申请号：US10191424
申请日：2002-07-08
申请人： Warren M. Farnworth , Alan G. Wood , James M. Wark , David R. Hembree , Syed Sajid Ahmad , Michael E. Hess , John O. Jacobson
发明人： Warren M. Farnworth , Alan G. Wood , James M. Wark , David R. Hembree , Syed Sajid Ahmad , Michael E. Hess , John O. Jacobson
IPC分类号： H01L21/44
CPC分类号： H01L23/544 , B33Y30/00 , B33Y80/00 , H01L21/563 , H01L23/293 , H01L23/3157 , H01L24/81 , H01L24/83 , H01L2223/5448 , H01L2224/05571 , H01L2224/05573 , H01L2224/11005 , H01L2224/1147 , H01L2224/11472 , H01L2224/16 , H01L2224/293 , H01L2224/81011 , H01L2224/8121 , H01L2224/81815 , H01L2224/83851 , H01L2924/00014 , H01L2924/01078 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/3512 , H01L2924/00 , H01L2224/05599
摘要： Methods of manufacturing semiconductor devices using permanent or temporary polymer layers having apertures to expose contact pads and cover the active surfaces of the semiconductor devices.

42. 发明授权

US06903443B2 Semiconductor component and interconnect having conductive members and contacts on opposing sides 失效
标题翻译：半导体元件和互连件具有导电构件和相对侧面上的触点
公开(公告)号：US06903443B2
公开(公告)日：2005-06-07
申请号：US10316349
申请日：2002-12-11
申请人： Warren M. Farnworth , Alan G. Wood , David R. Hembree
发明人： Warren M. Farnworth , Alan G. Wood , David R. Hembree
IPC分类号： H01L21/48 , H01L21/60 , H01L21/768 , H01L23/13 , H01L23/498 , H01L23/538 , H01L25/10 , H05K1/03 , H05K1/11 , H05K3/00 , H01L29/40
CPC分类号： H01L21/486 , H01L21/6835 , H01L21/76898 , H01L23/13 , H01L23/481 , H01L23/49827 , H01L23/5389 , H01L24/16 , H01L24/75 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/05569 , H01L2224/0557 , H01L2224/05573 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/16235 , H01L2224/73204 , H01L2224/75 , H01L2224/81801 , H01L2224/82039 , H01L2225/06513 , H01L2225/06541 , H01L2225/1005 , H01L2225/1058 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H05K1/0306 , H05K1/112 , H05K3/0029 , H05K3/0032 , H05K2201/09472 , H05K2201/0959 , H05K2201/09827 , H05K2201/09845 , H05K2201/10674 , H05K2201/10734 , H01L2924/00
摘要： A method for fabricating semiconductor components and interconnects includes the steps of providing a substrate, such as a semiconductor die, forming external contacts on opposing sides of the substrate by laser drilling vias through the substrate, and forming conductive members in the vias. The conductive members include enlarged terminal portions that are covered with a non-oxidizing metal. The method can be used to fabricate stackable semiconductor packages having integrated circuits in electrical communication with the external contacts. The method can also be used to fabricate interconnects for electrically engaging packages, dice and wafers for testing or for constructing electronic assemblies.
摘要翻译：一种用于制造半导体部件和互连的方法包括以下步骤：提供诸如半导体管芯的衬底，通过穿过衬底的激光钻孔通孔在衬底的相对侧上形成外部触点，以及在通孔中形成导电构件。导电构件包括被非氧化金属覆盖的扩大端子部分。该方法可用于制造具有与外部触点电连通的集成电路的可堆叠半导体封装。该方法还可用于制造用于电接合封装，裸片和晶片用于测试或构建电子组件的互连。

43. 发明授权

US06841883B1 Multi-dice chip scale semiconductor components and wafer level methods of fabrication 失效
标题翻译：多芯片尺寸半导体元件和晶圆级制造方法
公开(公告)号：US06841883B1
公开(公告)日：2005-01-11
申请号：US10403937
申请日：2003-03-31
申请人： Warren M. Farnworth , Alan G. Wood , William M. Hiatt , James M. Wark , David R. Hembree , Kyle K. Kirby , Pete A. Benson
发明人： Warren M. Farnworth , Alan G. Wood , William M. Hiatt , James M. Wark , David R. Hembree , Kyle K. Kirby , Pete A. Benson
IPC分类号： H01L21/56 , H01L21/60 , H01L21/768 , H01L21/98 , H01L23/31 , H01L23/48 , H01L25/065 , H01L29/40
CPC分类号： H01L21/561 , B33Y70/00 , B33Y80/00 , H01L21/563 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2221/68331 , H01L2224/02372 , H01L2224/0401 , H01L2224/05111 , H01L2224/05118 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05178 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05559 , H01L2224/05569 , H01L2224/05572 , H01L2224/05624 , H01L2224/05644 , H01L2224/05664 , H01L2224/05666 , H01L2224/13005 , H01L2224/13006 , H01L2224/13009 , H01L2224/13024 , H01L2224/13099 , H01L2224/16145 , H01L2224/73204 , H01L2224/97 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06582 , H01L2225/06596 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15312 , H01L2924/18161 , H01L2924/19015 , H01L2924/19041 , H01L2924/351 , H01L2924/207 , H01L2224/05552 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.
摘要翻译：半导体部件包括基模和层叠在基模上的二次模。基模具包括形成用于部件的内部信号传输系统的导电通孔，并允许二次管芯的电路侧接合到基座的后侧。该组件还包括与导电通孔电连通的基座芯片的电路侧上的端子触点阵列。该组件还可以包括在基模的背侧上的密封剂，其基本上封装次模，以及在用作保护层的基模的电路侧上的聚合物层，用于形成的用于固化的模板终端接触。一种用于制造该部件的方法包括将单个二次骰子接合到基底晶片上的基底骰子上，或将次晶片接合到基底晶片，或将单个二次骰子接合到单个基体骰子的步骤。

44. 发明授权

US06553276B2 Method of using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs 失效
标题翻译：集成电路（IC）使用数据的方法已经进行了修复，以选择IC将要进行的程序，例如额外修理
公开(公告)号：US06553276B2
公开(公告)日：2003-04-22
申请号：US10071961
申请日：2002-02-05
申请人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O Jacobson , James M. Wark , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O Jacobson , James M. Wark , Alan G. Wood
IPC分类号： G06F1900
CPC分类号： G06F11/006 , H01L2223/5444
摘要： An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the IC's. The ID codes of the IC's are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the IC's is then accessed, and additional repair procedures the IC's may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.
摘要翻译：一种集成电路（IC）制造过程中的发明方法，用于使用关于在探针上的IC进行的修复程序的数据，以确定是否在制造过程中稍后进行进一步的修复，包括将数据与每个的保险丝ID相关联地存储 IC的。例如，在制造过程中，IC的ID代码将自动读取，例如打开/短路测试。然后访问与IC的ID代码相关联存储的数据，并且根据访问的数据选择IC可能经历的附加修复过程。因此，例如，访问的数据可以指示IC不可修复，因此IC可以直接进入废料仓，而不必被查询以确定其是否可修复，如在传统IC制造过程中所必需的。

45. 发明授权

US06296171B1 Utilize ultrasonic energy to reduce the initial contact forces in known-good-die or permanent contact systems 失效
标题翻译：利用超声波能量来减少已知好的模具或永久接触系统中的初始接触力
公开(公告)号：US06296171B1
公开(公告)日：2001-10-02
申请号：US09416248
申请日：1999-10-12
申请人： David R. Hembree , Michael E. Hess , John O. Jacobson , Warren M. Farnworth , Alan G. Wood
发明人： David R. Hembree , Michael E. Hess , John O. Jacobson , Warren M. Farnworth , Alan G. Wood
IPC分类号： B23K106
CPC分类号： B23K20/10 , B23K2101/38
摘要： A machine and method for bonding puncture-type conductive contact members of an interconnect to the bond pads of a bare semiconductor die includes the use of one or two ultrasonic vibrators mounted to vibrate one or both of the die and interconnect. A short axial linear burst of ultrasonic energy enables the contact members to pierce hard oxide layers on the surfaces of the bond pads at a much lower compressive force and rapidly achieve full penetration depth.
摘要翻译：用于将互连的穿刺型导电接触构件接合到裸半导体管芯的接合焊盘的机器和方法包括使用安装成振动模具和互连中的一个或两者的一个或两个超声波振动器。超声能量的短轴向线性爆发使得接触构件能够以低得多的压缩力在接合焊盘的表面上刺穿硬氧化物层并且迅速地实现完全的穿透深度。

46. 发明授权

US06208157B1 Method for testing semiconductor components 有权
标题翻译：半导体元件测试方法
公开(公告)号：US06208157B1
公开(公告)日：2001-03-27
申请号：US09298769
申请日：1999-04-23
申请人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
发明人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
IPC分类号： G01R3102
CPC分类号： G01R1/0466 , G01R1/0433 , G01R1/0483
摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.
摘要翻译：提供了一种用于测试半导体部件的系统和方法。该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装在插座上用于容纳组件的载体。载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

47. 发明授权

US6091252A Method, apparatus and system for testing bumped semiconductor components 有权
标题翻译：用于测试碰撞半导体元件的方法，装置和系统
公开(公告)号：US6091252A
公开(公告)日：2000-07-18
申请号：US312381
申请日：1999-05-14
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood , David R. Hembree
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood , David R. Hembree
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R31/28 , G01R1/06 , G01R31/26
CPC分类号： G01R1/0466
摘要： A method, apparatus and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The apparatus includes an interconnect having patterns of contact members adapted to electrically contact the contact bumps. Each contact member includes an array of one or more electrically conductive projections in electrical communication with an associated conductor. The projections form contact members for retaining individual contact bumps on the semiconductor components. The projections can be pillars having angled faces covered with a conductive layer. Alternately the projections can be a material deposited on the substrate, or can be microbumps formed on multi layered tape bonded to the substrate. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.
摘要翻译：提供了一种用于与具有接触凸块的半导体部件建立临时电连通的方法，装置和系统。该装置包括具有适于电接触接触凸点的接触构件图案的互连。每个接触构件包括与相关导体电连通的一个或多个导电突起的阵列。突起形成接触构件，用于保持半导体部件上的各个接触凸块。突起可以是具有覆盖有导电层的成角度表面的柱。替代地，突起可以是沉积在基底上的材料，或者可以是在结合到基底的多层带上形成的微胶囊。互连可以用于晶片级测试系统中，用于测试包含在晶片上的骰子，或者在用于测试裸露骰子或凸起的芯片级封装的芯片级测试系统中。

48. 发明授权

US6060891A Probe card for semiconductor wafers and method and system for testing wafers 失效
标题翻译：半导体晶圆探针卡及晶圆测试方法及系统
公开(公告)号：US6060891A
公开(公告)日：2000-05-09
申请号：US797719
申请日：1997-02-11
申请人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
发明人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
IPC分类号： G01R1/073 , G01R31/28
CPC分类号： G01R1/073 , G01R31/2886
摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.
摘要翻译：提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。探针卡被配置用于与测试电路电连通的常规测试装置，例如晶片探测器处理器。探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。互连衬底可以由具有穿透突起的凸起接触构件的硅形成。或者，接触构件可以形成为用于测试凸起的晶片的凹陷。膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

49. 发明授权

US5931685A Interconnect for making temporary electrical connections with bumped semiconductor components 失效
标题翻译：互连用于与凸起的半导体元件进行临时电连接
公开(公告)号：US5931685A
公开(公告)日：1999-08-03
申请号：US867551
申请日：1997-06-02
申请人： David R. Hembree , John O. Jacobson , James M. Wark , Warren M. Farnworth , Salman Akram , Alan G. Wood
发明人： David R. Hembree , John O. Jacobson , James M. Wark , Warren M. Farnworth , Salman Akram , Alan G. Wood
IPC分类号： G01R1/04 , H01L21/00 , H01R12/04 , H05K3/32 , H01R9/09
CPC分类号： H01L21/67144 , G01R1/0408 , H05K3/326 , H01L2224/1601 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2224/81385
摘要： An interconnect and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The interconnect includes a substrate with patterns of contact members adapted to electrically contact the contact bumps. The substrate can be formed of a material such as ceramic, silicon, FR-4, or photo-chemically machineable glass. The contact members can be formed as recesses covered with conductive layers in electrical communication with conductors and terminal contacts on the substrate. Alternately, the contact members can be formed as projections adapted to penetrate the contact bumps, as microbumps with a rough textured surface, or as a deposited layer formed with recesses. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.
摘要翻译：提供了一种用于与具有接触凸块的半导体部件建立临时电连通的互连和系统。互连包括具有适于电接触接触凸块的接触部件图案的基板。衬底可由诸如陶瓷，硅，FR-4或光刻化学可加工玻璃的材料形成。接触构件可以形成为覆盖有与衬底上的导体和端子触点电连通的导电层的凹陷。或者，接触构件可以形成为适于穿透接触凸块的突起，作为具有粗糙纹理表面的微胶囊，或者形成为具有凹陷的沉积层。互连可以用于晶片级测试系统中，用于测试包含在晶片上的骰子，或者用于测试裸露的骰子或凸起的芯片级封装的芯片级测试系统。

50. 发明授权

US5907492A Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs 失效
公开(公告)号：US5907492A
公开(公告)日：1999-05-25
申请号：US871015
申请日：1997-06-06
申请人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O. Jacobson , James M. Wark , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Derek J. Gochnour , David R. Hembree , Michael E. Hess , John O. Jacobson , James M. Wark , Alan G. Wood
IPC分类号： G06F11/00 , G06F19/00
CPC分类号： G06F11/006 , H01L2223/5444
摘要： An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the IC's. The ID codes of the IC's are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the IC's is then accessed, and additional repair procedures the IC's may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.

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