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41. 发明申请

US20070161244A1 METHOD AND APPARATUS FOR POST SILICIDE SPACER REMOVAL 有权
标题翻译：硅胶分离器去除后的方法和装置
公开(公告)号：US20070161244A1
公开(公告)日：2007-07-12
申请号：US11164417
申请日：2005-11-22
申请人： Brian J. Greene , Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Siddhartha Panda , Kern Rim , Young Way Teh
发明人： Brian J. Greene , Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Siddhartha Panda , Kern Rim , Young Way Teh
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31116 , H01L21/31144 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.
摘要翻译：后硅化物间隔物去除的方法（和装置）包括通过使用氧化物层和氮化物层中的至少一种来防止对硅化物间隔物的损害。

42. 发明授权

US07141854B2 Double-gated silicon-on-insulator (SOI) transistors with corner rounding 有权
标题翻译：双栅绝缘体（SOI）晶体管，带圆角
公开(公告)号：US07141854B2
公开(公告)日：2006-11-28
申请号：US11174857
申请日：2005-07-05
申请人： Yong Meng Lee , Da Jin , David Vigar
发明人： Yong Meng Lee , Da Jin , David Vigar
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L23/62
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/7854 , H01L29/78648 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps, inter alia. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer, having an opening defining a gate, is formed over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer. An undercut is formed into the undercut lower SOI oxide layer and the exposed gate area portion of the oxide layer is removed. The portion of the rounded oxide layer within the gate area is removed and a conformal oxide layer is formed over a part of the structure. A gate is formed within the second patterned dummy layer opening and the patterned dummy layer is removed to form the double gated transistor.
摘要翻译：形成具有圆形有源区域以提高GOI和漏电流控制的双门控晶体管的方法尤其包括以下步骤。图案化SOI衬底，并且在图案化的上SOI硅层的暴露侧壁上形成圆形氧化物层。在暴露的图案化的顶部氧化物层和上部SOI硅层的暴露部分之上形成具有限定栅极的开口的虚设层。在底切下面的SOI氧化物层中形成底切，去除氧化物层的暴露的栅极区域部分。去除栅极区域内的圆形氧化物层的部分，并且在该结构的一部分上形成共形氧化物层。在第二图案化虚拟层开口内形成栅极，去除图案化虚拟层以形成双门控晶体管。

43. 发明授权

US06541327B1 Method to form self-aligned source/drain CMOS device on insulated staircase oxide 失效
标题翻译：在绝缘阶梯氧化物上形成自对准源极/漏极CMOS器件的方法
公开(公告)号：US06541327B1
公开(公告)日：2003-04-01
申请号：US09760123
申请日：2001-01-16
申请人： Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
发明人： Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
IPC分类号： H01L218238
CPC分类号： H01L29/66492 , H01L21/823814 , H01L29/41783 , H01L29/665 , H01L29/66575
摘要： A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard mask. A first insulating layer is formed over the substrate and the gate structure. A resist layer is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. We etch the insulating layer through the opening in the resist layer. The etching removes a first thickness of the insulating layer to form a source/drain (S/D) opening. We remove the first spacers and hardmask to form a source/drain (S/D) contact opening. We implant ions into the substrate through the source/drain (S/D) contact opening to form lightly doped drain regions. We form second spacers on the sidewalls of the gate electrode and the gate dielectric and on the sidewalls of the insulating layer in the source/drain (S/D) contact opening and the source/drain (S/D) opening. A conductive layer is deposited over the gate electrode, the insulating layer. The conductive layer is planarized to exposed the insulating layer to form elevated source/drain (S/D) blocks on a staircase shape insulating layer.
摘要翻译：一种在绝缘层中的阶梯形开口形成升高的源极/漏极（S / D）的方法。栅极结构形成在衬底上。栅极结构优选由栅极电介质层，栅电极，第一间隔物和硬掩模组成。在衬底和栅极结构之上形成第一绝缘层。形成抗蚀剂层，其具有在栅极结构上方的开口以及与栅极结构相邻的横向区域。我们通过抗蚀剂层中的开口蚀刻绝缘层。蚀刻去除绝缘层的第一厚度以形成源极/漏极（S / D）开口。我们移除第一个垫片和硬掩模以形成一个源极/漏极（S / D）接触开口。我们通过源极/漏极（S / D）接触开口将离子注入到衬底中，以形成轻掺杂的漏极区。我们在源极/漏极（S / D）接触开口和源极/漏极（S / D）开口中的栅电极和栅极电介质的侧壁和绝缘层的侧壁上形成第二间隔物。在栅电极，绝缘层上沉积导电层。导电层被平坦化以暴露绝缘层，以在阶梯形绝缘层上形成升高的源极/漏极（S / D）块。

44. 发明授权

US06436770B1 Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation 失效
标题翻译：通过使用选择性外延和使用注入的源极/漏极首先形成沟道来控制垂直晶体管的沟道长度的方法
公开(公告)号：US06436770B1
公开(公告)日：2002-08-20
申请号：US09721720
申请日：2000-11-27
申请人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
发明人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
IPC分类号： H01L21332
CPC分类号： H01L29/7827 , H01L29/42356 , H01L29/66666
摘要： A method for a vertical MOS transistor whose vertical channel width can be accurately defined and controlled. Isolation regions are formed in a substrate. The isolation regions defining an active area. Then, we form a source region in the active area. A dielectric layer is formed over the active area and the isolation regions. We form a barrier layer over the dielectric layer. We form an opening in the barrier layer. A gate layer is formed in the opening. We form an insulating layer over the conductive layer and the barrier layer. We form a gate opening through the insulating layer, the gate layer and the dielectric layer to expose the source region. Gate dielectric spacers are formed over the sidewalls of the gate layer. Then, we form a conductive plug filling the gate opening. The insulating layer is removed. We form a drain region in top and side portions of the conductive plug and form doped gate regions in the gate layer. The remaining portions of the conductive plug comprise a channel region. A channel length is between the top of the source region and the drain region. We form an interlevel dielectric layer over the barrier layer, the gate layer, and the conductive plug. Contacts are formed through the interlevel dielectric layer to the doped gate regions, the drain region and the source region.
摘要翻译：一种垂直MOS晶体管的方法，其垂直沟道宽度可以被精确地限定和控制。在衬底中形成隔离区。隔离区限定有效区域。然后，我们在活动区域中形成一个源区域。在有源区域和隔离区域上形成介电层。我们在电介质层上形成阻挡层。我们在屏障层形成一个开口。在开口中形成栅极层。我们在导电层和阻挡层上形成绝缘层。我们通过绝缘层，栅极层和电介质层形成栅极开口以暴露源极区域。栅极电介质隔离物形成在栅极层的侧壁上。然后，我们形成一个填充门开口的导电塞。绝缘层被去除。我们在导电插塞的顶部和侧部形成漏极区，并在栅极层中形成掺杂的栅极区。导电插塞的其余部分包括沟道区域。沟道长度在源极区域的顶部和漏极区域之间。我们在阻挡层，栅极层和导电插塞上形成层间电介质层。通过层间介质层与掺杂栅极区，漏极区和源极区形成触点。

45. 发明授权

US06436754B1 Selective salicide process by reformation of silicon nitride sidewall spacers 有权
标题翻译：选择性的自对准硅化物工艺通过改造氮化硅侧壁间隔件
公开(公告)号：US06436754B1
公开(公告)日：2002-08-20
申请号：US09863221
申请日：2001-05-24
申请人： Yong Meng Lee
发明人： Yong Meng Lee
IPC分类号： H01L218234
CPC分类号： H01L27/11526 , H01L27/11543 , H01L29/665 , H01L29/66515 , H01L29/6659
摘要： A new method of forming selective salicide structures is described whereby robust salicide structures are formed on exposed logic FET's, while blocking salicide formation on memory FET's. Thus, yielding logic FET's with robust salicide structures which exhibit low sheet rho lines and contacts, while blocking salicide formation on the sensitive memory FET's which operate at low voltage and have low leakage, shallow junctions. A conformal layer of thick silicon nitride in conjunction with a salicide blockout mask forms robust selective salicide structures. These structures exhibit low leakage and lack leakage problems caused by bridging, silicide ribbons or stringers.
摘要翻译：描述了一种形成选择性自对准硅化物结构的新方法，其中在暴露的逻辑FET上形成稳固的自对准硅化物结构，同时阻挡存储器FET的自对准硅化物形成。因此，产生具有强烈的自对准硅化物结构的逻辑FET，其表现出低的薄片rho线和触点，同时阻挡在低电压操作并且具有低泄漏，浅结的敏感存储器FET上的自对准硅化物形成。与硅化物堵塞掩模结合的厚氮化硅的保形层形成鲁棒的选择性硅化物结构。这些结构表现出低的泄漏和缺乏由桥接，硅化物带或桁条引起的泄漏问题。

46. 发明授权

US06372569B1 Selective formation of hydrogen rich PECVD silicon nitride for improved NMOS transistor performance 有权
标题翻译：选择性形成富氢PECVD氮化硅，以改善NMOS晶体管性能
公开(公告)号：US06372569B1
公开(公告)日：2002-04-16
申请号：US09483035
申请日：2000-01-18
申请人： Yong Meng Lee , Gao Feng , Yunqzang Zhang , Ravi Sundaresan
发明人： Yong Meng Lee , Gao Feng , Yunqzang Zhang , Ravi Sundaresan
IPC分类号： H01L218238
CPC分类号： H01L21/823814
摘要： A method of selective formation of SiN layer in a semiconductor device comprising the following steps. A semiconductor structure having at least one PMOS transistor and one NMOS transistor formed therein is provided. The PMOS and NMOS transistors each have source/drain regions, a gate, and salicide contact regions. An undoped silicate glass (USG) layer is deposited over the semiconductor structure and the PMOS and NMOS transistors. An H2-rich PECVD silicon nitride layer is deposited over the undoped silicate glass layer and over the PMOS and NMOS transistors. The H2-rich PECVD silicon nitride layer is patterned, etched, and removed from over the PMOS transistor. An inter-level dielectric (ILD) layer is formed over the structure. The ILD layer is densified whereby hydrogen diffuses from the H2-rich PECVD silicon nitride layer overlying the NMOS transistor into the source/drain of the NMOS transistor.
摘要翻译：一种在半导体器件中选择性地形成SiN层的方法，包括以下步骤。提供具有形成在其中的至少一个PMOS晶体管和一个NMOS晶体管的半导体结构。 PMOS和NMOS晶体管各自具有源极/漏极区域，栅极和自对准硅化物接触区域。在半导体结构和PMOS和NMOS晶体管上沉积未掺杂的硅酸盐玻璃（USG）层。富含H 2 O的PECVD氮化硅层沉积在未掺杂的硅酸盐玻璃层上并在PMOS和NMOS晶体管之上。从富于PMOS晶体管的图案化，蚀刻和去除富H2的PECVD氮化硅层。在该结构上形成层间电介质（ILD）层。 ILD层被致密化，由此氢从NMOS晶体管上的富H 2 PECVD氮化硅层扩散到NMOS晶体管的源极/漏极。

47. 发明授权

US06313008B1 Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon 失效
标题翻译：使用微加工技术形成气球形STI以去除重掺杂硅的方法
公开(公告)号：US06313008B1
公开(公告)日：2001-11-06
申请号：US09768486
申请日：2001-01-25
申请人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
发明人： Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： The invention describes three embodiments of methods for forming a balloon shaped STI trench. The first embodiment begins by forming a barrier layer over a substrate. An isolation opening is formed in the barrier layer. Next, ions are implanted into said substrate through said isolation opening to form a Si damaged or doped first region. The first region is selectively etching to form a hole. The hole is filled with an insulating material to form a balloon shaped shallow trench isolation (STI) region. The substrate has active areas between said balloon shaped shallow trench isolation (STI) regions. The second embodiment differs from the first embodiment by forming a trench in the substrate before the implant. The third embodiment forms a liner in the trench before an isotropic etch of the substrate through the trench.
摘要翻译：本发明描述了形成球形STI沟槽的方法的三个实施例。第一实施例开始于在衬底上形成阻挡层。在阻挡层中形成隔离开口。接下来，通过所述隔离开口将离子注入到所述衬底中，以形成Si损伤或掺杂的第一区域。第一区域是选择性蚀刻以形成孔。孔用绝缘材料填充以形成气球形的浅沟槽隔离（STI）区域。衬底在所述球形浅沟槽隔离（STI）区域之间具有有效区域。第二实施例通过在植入物之前在衬底中形成沟槽而与第一实施例不同。在通过沟槽对衬底进行各向同性蚀刻之前，第三实施例在沟槽中形成衬垫。

48. 发明授权

US08106462B2 Balancing NFET and PFET performance using straining layers 失效
标题翻译：使用应变层平衡NFET和PFET性能
公开(公告)号：US08106462B2
公开(公告)日：2012-01-31
申请号：US12687374
申请日：2010-01-14
申请人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
发明人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L29/7843
摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
摘要翻译：集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。该对互补晶体管包括第一晶体管和第二晶体管。该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

49. 发明授权

US08053327B2 Method of manufacture of an integrated circuit system with self-aligned isolation structures 有权
标题翻译：具有自对准隔离结构的集成电路系统的制造方法
公开(公告)号：US08053327B2
公开(公告)日：2011-11-08
申请号：US11614961
申请日：2006-12-21
申请人： Shailendra Mishra , Lee Wee Teo , Yong Meng Lee , Zhao Lun , Chung Woh Lai , Shyue Seng Tan , Jeffrey Chee , Johnny Widodo
发明人： Shailendra Mishra , Lee Wee Teo , Yong Meng Lee , Zhao Lun , Chung Woh Lai , Shyue Seng Tan , Jeffrey Chee , Johnny Widodo
IPC分类号： H01L21/76 , H01L21/00
CPC分类号： H01L21/76232 , H01L21/76283 , H01L21/823481
摘要： An integrated circuit system is provided including providing a substrate, forming an isolation structure base in the substrate without removal of the substrate, and forming a first transistor in the substrate next to the isolation structure base.
摘要翻译：提供一种集成电路系统，包括提供衬底，在衬底中形成隔离结构基底而不去除衬底，以及在隔离结构基底旁边的衬底中形成第一晶体管。

50. 发明授权

US07999325B2 Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS 有权
标题翻译：腐蚀后去除间隔物的方法，以增强接触蚀刻停止衬垫在MOS上的应力
公开(公告)号：US07999325B2
公开(公告)日：2011-08-16
申请号：US12241073
申请日：2008-09-30
申请人： Young Way Teh , Yong Meng Lee , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , John Sudijono , Hui Peng Koh , Liang Choo Hsia
发明人： Young Way Teh , Yong Meng Lee , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , John Sudijono , Hui Peng Koh , Liang Choo Hsia
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/823864
摘要： An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.
摘要翻译：从NMOS晶体管的栅极去除间隔物的示例性过程。在NMOS和PMOS晶体管和衬底上形成应力产生层。在一个实施例中，栅极上的间隔物被去除，使得应力层更靠近器件的通道。应力产生层优选为拉伸氮化物层。应力产生层优选为接触蚀刻停止衬层。在一个实施例中，在形成应力产生层之前，栅极，源极和漏极区域之前具有硅化物层。该实施例改善了NMOS晶体管的性能。

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