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41. 发明申请

US20050032361A1 High aspect ratio contact structure with reduced silicon consumption 失效
公开(公告)号：US20050032361A1
公开(公告)日：2005-02-10
申请号：US10931854
申请日：2004-09-01
申请人： Ammar Derraa , Sujit Sharan , Paul Castrovillo
发明人： Ammar Derraa , Sujit Sharan , Paul Castrovillo
IPC分类号： H01L21/285 , H01L21/4763 , H01L21/768 , H01L29/45 , H01L21/44
CPC分类号： H01L21/76846 , H01L21/28518 , H01L21/28556 , H01L21/76843 , H01L21/76855 , H01L21/76868 , H01L21/76877 , H01L29/456
摘要： A high aspect ratio contact structure formed over a junction region in a silicon substrate comprises a titanium interspersed with titanium silicide layer that is deposited in the contact opening and directly contacts an upper surface of the substrate. Silicon-doping of CVD titanium, from the addition of SiH4 during deposition, reduces consumption of substrate silicon during the subsequent silicidation reaction in which the titanium reacts with silicon to form a titanium silicide layer that provides low resistance electrical contacts between the junction region and the silicon substrate. The contact structure further comprises a titanium nitride contact fill that is deposited in the contact opening and fills substantially the entire contact opening.

42. 发明授权

US06835654B2 Methods of forming an electrically conductive line 失效
标题翻译：形成导电线的方法
公开(公告)号：US06835654B2
公开(公告)日：2004-12-28
申请号：US10315429
申请日：2002-12-09
申请人： Gurtej S. Sandhu , Sujit Sharan
发明人： Gurtej S. Sandhu , Sujit Sharan
IPC分类号： H01L214763
CPC分类号： H01L21/02667 , C30B1/02 , C30B29/34 , H01L21/2022 , H01L21/28061 , H01L21/28247 , H01L21/28518 , H01L21/32053 , H01L29/7842
摘要： Methods of forming an electrically conductive line include providing a stress inducing material within or a compressive stress inducing layer operatively adjacent a crystalline material of a first crystalline phase. In addition, such methods include annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. Some methods also include providing stress inducing materials into a refractory metal layer. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials include Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSix.
摘要翻译：形成导电线的方法包括在与第一结晶相的结晶材料可操作地相邻处提供应力诱导材料或压应力诱导层。此外，这些方法包括在有效地将其转变为第二结晶相的条件下退火第一结晶相的结晶材料。一些方法还包括将应力诱导材料提供到难熔金属层中。示例性压缩应力诱导层包括SiO 2和Si 3 N 4，而示例的应力诱导材料包括Ge，W和Co。当压应力诱导材料设置在提供结晶相材料的晶片的同一侧时，具有小于第一相结晶材料的热膨胀系数。具有两相的实例和优选结晶相材料是难熔金属硅化物，例如TiSix。

43. 发明授权

US06815344B2 Methods of forming an electrically conductive line 失效
标题翻译：形成导电线的方法
公开(公告)号：US06815344B2
公开(公告)日：2004-11-09
申请号：US10061738
申请日：2002-01-31
申请人： Gurtej S. Sandhu , Sujit Sharan
发明人： Gurtej S. Sandhu , Sujit Sharan
IPC分类号： H01L2144
CPC分类号： H01L21/02667 , C30B1/02 , C30B29/34 , H01L21/2022 , H01L21/28061 , H01L21/28247 , H01L21/28518 , H01L21/32053 , H01L29/7842
摘要： A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material. Where the compressive stress inducing material is provided on the opposite side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is greater than the first phase crystalline material. Example and preferred crystalline phase materials having two phases are refractory metal suicides, such as TiSix.
摘要翻译：形成结晶相材料的方法包括：a）在第一结晶相的结晶材料内部或在其中邻近的第一结晶相中提供应力诱导材料; 和b）在有效地将其转变成第二结晶相的条件下退火第一结晶相的结晶材料。应力诱导材料优选在与第二结晶相退火期间在第一结晶相内诱导压应力，以降低所需的活化能以产生更致密的第二结晶相。示例性压缩应力诱导层包括SiO 2和Si 3 N 4，而用于提供层的示例性应力诱导材料是Ge，W和Co。其中压应力诱导材料设置在提供结晶相材料的晶片的同一侧上，提供的热膨胀系数小于第一相结晶材料。在压应力诱导材料设置在提供结晶相材料的晶片的相对侧上的情况下，其被设置为具有大于第一相结晶材料的热膨胀系数。具有两相的实例和优选结晶相材料是难熔金属硅化物，例如TiSix。

44. 发明授权

US06727173B2 Semiconductor processing methods of forming an utilizing antireflective material layers, and methods of forming transistor gate stacks 有权
标题翻译：形成利用抗反射材料层的半导体加工方法以及形成晶体管栅叠层的方法
公开(公告)号：US06727173B2
公开(公告)日：2004-04-27
申请号：US09891570
申请日：2001-06-25
申请人： Gurtej S. Sandhu , Sujit Sharan
发明人： Gurtej S. Sandhu , Sujit Sharan
IPC分类号： H01L214763
CPC分类号： G03F7/091 , H01L21/0214 , H01L21/02211 , H01L21/02274 , H01L21/0276 , H01L21/28123 , H01L21/3145
摘要： In one aspect, the invention includes a semiconductor processing method comprising exposing silicon, nitrogen and oxygen in gaseous form to a high density plasma during deposition of a silicon, nitrogen and oxygen containing solid layer over a substrate. In another aspect, the invention includes a gate stack forming method, comprising: a) forming a polysilicon layer over a substrate; b) forming a metal silicide layer over the polysilicon layer; c) depositing an antireflective material layer over the metal silicide utilizing a high density plasma; d) forming a layer of photoresist over the antireflective material layer; e) photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist; and f) transferring a pattern from the patterned masking layer to the antireflective material layer, metal silicide layer and polysilicon layer to pattern the antireflective material layer, metal silicide layer and polysilicon layer into a gate stack.
摘要翻译：在一个方面，本发明包括一种半导体处理方法，包括在衬底上沉积含硅，含氮和氧的固体层时将硅，氮和氧气体暴露于高密度等离子体。在另一方面，本发明包括一种栅堆叠形成方法，包括：a）在衬底上形成多晶硅层; b）在所述多晶硅层上形成金属硅化物层; c）利用高密度等离子体在金属硅化物上沉积防反射材料层; d）在抗反射材料层上形成一层光致抗蚀剂; e）光刻地图案化所述光致抗蚀剂层以从所述光致抗蚀剂层形成图案化掩模层; 以及f）将图案从图案化掩模层转移到抗反射材料层，金属硅化物层和多晶硅层，以将防反射材料层，金属硅化物层和多晶硅层图案化成栅叠层。

45. 发明授权

US06705246B2 RF powered plasma enhanced chemical vapor deposition reactor and methods of effecting plasma enhanced chemical vapor deposition 有权
标题翻译： RF功率等离子体增强化学气相沉积反应器和实现等离子体增强化学气相沉积的方法
公开(公告)号：US06705246B2
公开(公告)日：2004-03-16
申请号：US10047382
申请日：2002-01-14
申请人： Sujit Sharan , Gurtej S. Sandhu , Paul Smith , Mei Chang
发明人： Sujit Sharan , Gurtej S. Sandhu , Paul Smith , Mei Chang
IPC分类号： C23C1600
CPC分类号： H01J37/32174 , C23C16/505 , H01J37/32082 , H01J37/321 , Y10S438/961
摘要： Plasma enhanced chemical vapor deposition (PECVD) reactors and methods of effecting the same are described. In accordance with a preferred implementation, a reaction chamber includes first and second electrodes operably associated therewith. A single RF power generator is connected to an RF power splitter which splits the RF power and applies the split power to both the first and second electrodes. Preferably, power which is applied to both electrodes is in accordance with a power ratio as between electrodes which is other than a 1:1 ratio. In accordance with one preferred aspect, the reaction chamber comprises part of a parallel plate PECVD system. In accordance with another preferred aspect, the reaction chamber comprises part of an inductive coil PECVD system. The power ratio is preferably adjustable and can be varied. One manner of effecting a power ratio adjustment is to vary respective electrode surface areas. Another manner of effecting the adjustment is to provide a power splitter which enables the output power thereof to be varied. PECVD processing methods are described as well.
摘要翻译：描述了等离子体增强化学气相沉积（PECVD）反应器及其实现方法。根据优选的实施方案，反应室包括与其可操作地相关联的第一和第二电极。单个RF功率发生器连接到RF功率分配器，RF功率分配器分离RF功率并将分裂功率施加到第一和第二电极。优选地，施加到两个电极的功率与不同于1:1的电极之间的功率比一致。根据一个优选方面，反应室包括平行板PECVD系统的一部分。根据另一个优选的方面，反应室包括感应线圈PECVD系统的一部分。功率比优选是可调节的并且可以变化。实现功率比调整的一种方式是改变各个电极表面积。实现调整的另一种方式是提供能够改变输出功率的功率分配器。还描述了PECVD处理方法。

46. 发明授权

US06642620B1 Integrated circuits having low resistivity contacts and the formation thereof using an in situ plasma doping and clean 有权
标题翻译：具有低电阻率触点的集成电路及其使用原位等离子体掺杂和清洁的形成
公开(公告)号：US06642620B1
公开(公告)日：2003-11-04
申请号：US09839379
申请日：2001-04-20
申请人： Sujit Sharan , Gurtej S. Sandhu
发明人： Sujit Sharan , Gurtej S. Sandhu
IPC分类号： H01L2348
CPC分类号： H01L21/28518 , H01L21/02046 , H01L21/76814 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Contact areas comprising doped semiconductor material at the bottom of contact holes are cleaned in a hot hydrogen plasma and exposed in situ during and/or separately from the hot hydrogen clean to a plasma containing the same dopant species as in the semiconductor material so as to partially, completely, or more than completely offset any loss of dopant due to the hot hydrogen clean. A protective conductive layer such as a metal silicide is then formed over the contact area in situ. The resulting integrated circuit has contacts with interfaces such as a silicide interfaces to contact areas having a particularly favorable dopant profile and concentration adjacent the silicide interfaces.
摘要翻译：接触孔底部包括掺杂半导体材料的接触区域在热氢等离子体中进行清洗，并在热氢清洗期间和/或与热氢清洗器分开暴露于包含与半导体材料相同的掺杂物质的等离子体中，，完全或更多地完全抵消由于热氢清洁而导致的掺杂剂的任何损失。然后在接触区域上原位形成诸如金属硅化物的保护性导电层。所得到的集成电路具有与诸如硅化物界面的接口与具有特别有利的掺杂剂分布和邻近硅化物界面的浓度的接触区的接触。

47. 发明授权

US06627465B2 System and method for detecting flow in a mass flow controller 失效
标题翻译：用于检测质量流量控制器中流量的系统和方法
公开(公告)号：US06627465B2
公开(公告)日：2003-09-30
申请号：US09945161
申请日：2001-08-30
申请人： Gurtej Singh Sandhu , Sujit Sharan , Neal R. Rueger , Allen P. Mardian
发明人： Gurtej Singh Sandhu , Sujit Sharan , Neal R. Rueger , Allen P. Mardian
IPC分类号： H01L2166
CPC分类号： G01F1/40 , G01F1/42 , G01P13/0006 , G01P13/0013 , G01P13/0033 , G05D7/0635 , Y10T29/41 , Y10T137/0396 , Y10T137/7722 , Y10T137/775 , Y10T137/8242
摘要： Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to monitor flow through the MFC and to immediately or nearly immediately detect a flow failure. In one embodiment of the present invention, a novel MFC is provided. The MFC includes an orifice, a mass flow control gate, an actuator and a gate position sensor. The actuator moves the control gate to control flow through the orifice. The gate position sensor determines the gate position and/or gate movement to monitor flow and immediately or nearly immediately detect a flow failure. According to one embodiment of the present invention, the gate position sensor includes a transmitter for transmitting a signal and a receiver for receiving the signal such that the receiver provides an indication of the position of the gate based on the signal received. Other embodiments of the gate position sensor are described herein, as well as systems and methods that incorporate the novel MFC within a semiconductor manufacturing process.
摘要翻译：提供了用于检测质量流量控制器（MFC）中的流量的系统和方法。 MFC中的门的位置被感测或以其他方式确定以监视通过MFC的流动并立即或几乎立即检测到流动故障。在本发明的一个实施例中，提供了一种新颖的MFC。 MFC包括孔口，质量流量控制门，致动器和门位置传感器。致动器移动控制门以控制通过孔口的流动。门位置传感器确定门位置和/或门移动以监视流量并立即或几乎立即检测到流动故障。根据本发明的一个实施例，门位置传感器包括用于发送信号的发射机和用于接收信号的接收机，使得接收机基于所接收的信号提供门的位置的指示。这里描述了门位置传感器的其他实施例，以及在半导体制造过程中并入新颖的MFC的系统和方法。

48. 发明授权

US06368988B1 Combined gate cap or digit line and spacer deposition using HDP 失效
公开(公告)号：US06368988B1
公开(公告)日：2002-04-09
申请号：US09354572
申请日：1999-07-16
申请人： Weimin Li , Sujit Sharan , Gurtej Sandhu
发明人： Weimin Li , Sujit Sharan , Gurtej Sandhu
IPC分类号： H01L21318
CPC分类号： H01L29/6656 , C23C16/345 , C23C16/402 , H01L21/02164 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/31612 , H01L21/3185 , H01L21/76832 , H01L21/76834 , H01L21/76885
摘要： A method for fabricating gate electrodes and gate interconnects with a protective silicon oxide or silicon nitride cap and spacer formed by high density plasma chemical vapor deposition (HDPCVD). Silicon oxide or silicon nitride is deposited in a reaction zone of a HDPCVD reactor while providing two or more selected substrate bias powers, source powers and/or selected gas mixtures to tailor the shape and thickness of the film for desired applications. In one embodiment, a low bias power of below 500 Watts is provided in a first stage HDPCVD and the bias power is then increased to between 500 and 3000 Watts for a second stage to produce a protective film having thin sidewall spacers for enhanced semiconductor device density and a relatively thick cap.

49. 发明授权

US06284651B1 Method for forming a contact having a diffusion barrier 有权
标题翻译：用于形成具有扩散阻挡层的接触的方法
公开(公告)号：US06284651B1
公开(公告)日：2001-09-04
申请号：US09273118
申请日：1999-03-19
申请人： Sujit Sharan , Varatharajan Nagabushnam
发明人： Sujit Sharan , Varatharajan Nagabushnam
IPC分类号： H01L214763
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/28525 , H01L21/76843 , H01L21/76856 , H01L21/76877 , H01L23/485 , H01L23/53271 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a novel contact structure comprising an underlying layer of titanium silicide, an intermediate layer of titanium boride, and an overlying layer of polysilicon. Also disclosed is a method for forming the contact structure which comprises depositing a titanium layer in the bottom of a contact opening having oxide insulation sidewalls, forming an overlying layer of polysilicon above the titanium layer, and annealing the two layers together. The resulting contact structure is formed with fewer steps than contact structures of the prior art and without the need for additional steps to achieve uniform sidewall coverage, due to high adhesion of the overlying layer of polysilicon with oxide insulation sidewalls of the contact opening. The contact structure has low contact resistance, and provides a suitable diffusion barrier due to a high melting point.
摘要翻译：公开了一种新颖的接触结构，其包括硅化钛的下层，硼化钛的中间层和多晶硅的上覆层。还公开了一种用于形成接触结构的方法，其包括在具有氧化物绝缘侧壁的接触开口的底部沉积钛层，在钛层上方形成上覆多层多晶硅，并将两层退火在一起。所形成的接触结构由现有技术的接触结构较少的步骤形成，并且不需要另外的步骤来实现均匀的侧壁覆盖，这是由于多晶硅的上覆层与接触开口的氧化物绝缘侧壁的高粘合性。接触结构具有低接触电阻，并且由于高熔点而提供合适的扩散阻挡层。

50. 发明授权

US06255209B1 Methods of forming a contact having titanium formed by chemical vapor deposition 有权
标题翻译：形成通过化学气相沉积形成的具有钛的接触的方法
公开(公告)号：US06255209B1
公开(公告)日：2001-07-03
申请号：US09376023
申请日：1999-08-19
申请人： Trung T. Doan , Gurtej Singh Sandhu , Kirk Prall , Sujit Sharan
发明人： Trung T. Doan , Gurtej Singh Sandhu , Kirk Prall , Sujit Sharan
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , C23C16/02 , C23C16/0236 , C23C16/42 , H01L21/28518 , H01L21/28556 , H01L21/76855
摘要： Methods are provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). The methods include forming titanium in the contact. One method includes forming titanium by combining a titanium precursor in the presence of hydrogen, H2. Another method includes forming titanium by combining titanium tetrachloride, TiCl4, in the presence of hydrogen. A further method includes forming titanium by combining tetradimethyl amino titanium, Ti(N(CH3)2)4, in the presence of hydrogen.
摘要翻译：提供了通过化学气相沉积（CVD）在集成电路中形成接触的方法。所述方法包括在接触中形成钛。一种方法包括通过在氢气存在下将钛前体组合而形成钛。另一种方法包括在氢的存在下将四氯化钛，TiCl 4组合形成钛。另一种方法包括在氢的存在下，通过组合四（二甲基氨基）钛，Ti（N（CH 3）2）4形成钛。

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