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41. 发明授权

US06911807B2 Method and circuit for limiting a pumped voltage 有权
标题翻译：用于限制泵送电压的方法和电路
公开(公告)号：US06911807B2
公开(公告)日：2005-06-28
申请号：US10823301
申请日：2004-04-12
申请人： Ronnie M. Harrison
发明人： Ronnie M. Harrison
IPC分类号： H02M3/07 , G05F1/40 , G05F1/618
CPC分类号： H02M3/073
摘要： A method and circuit control the value of generated voltage derived from a supply voltage as the value of the supply voltage varies, such as during burn-in of an integrated circuit. A voltage generation circuit includes a generator circuit that receives a supply voltage and has a reference node and develops an output voltage from the supply voltage, the output voltage having a value that is a function of a reference voltage applied on the reference node. A coupling circuit receives the supply voltage and operates in response to a voltage control signal to vary an electronic coupling of the supply voltage to the reference node to thereby adjust the value of the reference voltage. A voltage sensing circuit develops the voltage control signal that is applied to the coupling circuit in response to the reference voltage.
摘要翻译：当集成电路的老化期间，电源电压的值变化时，方法和电路控制从电源电压导出的产生电压的值。电压产生电路包括发生器电路，其接收电源电压并具有参考节点并且从所述电源电压产生输出电压，所述输出电压具有作为施加在所述参考节点上的参考电压的函数的值。耦合电路接收电源电压并响应于电压控制信号而操作，以改变电源电压与参考节点的电子耦合，从而调整参考电压的值。电压感测电路响应于参考电压产生施加到耦合电路的电压控制信号。

42. 发明授权

US06842399B2 Delay lock loop circuit useful in a synchronous system and associated methods 失效
标题翻译：延迟锁定环路电路在同步系统中有用，并且有相关的方法
公开(公告)号：US06842399B2
公开(公告)日：2005-01-11
申请号：US10706003
申请日：2003-11-12
申请人： Ronnie M. Harrison
发明人： Ronnie M. Harrison
IPC分类号： G11C8/18 , H03K23/54 , H03K23/66 , H03L7/081 , H03L7/085 , H03L7/089 , H03L7/095 , G11C8/00 , H03L7/06
CPC分类号： G11C8/18 , H03K23/542 , H03K23/66 , H03L7/0814 , H03L7/085 , H03L7/0896 , H03L7/095 , H03L2207/18
摘要： A method and circuitry for a delay lock loop useful in synchronizing the accessing of a memory array with a system clock is disclosed. In a preferred embodiment, the delay lock loop includes a variable delay element. The delay of the variable delay element is initially set to a minimum delay value. The system clock is then frequency divided and sent to the variable delay element, the output of which will ultimately be used to access the memory array in a synchronized manner with the system clock. The frequency divided clock and the output of the variable delay element are input to a phase detector, which creates a control signal for adjusting the delay of the variable delay element. After the signals are determined to be locked by the phase detector, an undivided clock signal version of the clock signal is sent to the variable delay element, and a frequency divided version of the output of the variable delay element is sent to the phase detector in lieu of the previous output of the variable delay element.
摘要翻译：公开了一种用于使存储器阵列与系统时钟的访问同步的延迟锁定循环的方法和电路。在优选实施例中，延迟锁定环包括可变延迟元件。可变延迟元件的延迟最初设置为最小延迟值。系统时钟然后被分频并发送到可变延迟元件，其输出将最终用于以与系统时钟同步的方式访问存储器阵列。分频时钟和可变延迟元件的输出被输入到相位检测器，其产生用于调整可变延迟元件的延迟的控制信号。在信号被相位检测器确定为锁定之后，时钟信号的未分割时钟信号版本被发送到可变延迟元件，并且可变延迟元件的输出的分频版本被发送到相位检测器代替可变延迟元件的先前输出。

43. 发明授权

US06801989B2 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same 失效
标题翻译：用于调整时钟信号与与该时钟信号一起发送的相应数字信号之间的定时偏移的方法和系统，以及使用该时钟信号的存储器件和计算机系统
公开(公告)号：US06801989B2
公开(公告)日：2004-10-05
申请号：US09896030
申请日：2001-06-28
申请人： Brian Johnson , Ronnie M. Harrison
发明人： Brian Johnson , Ronnie M. Harrison
IPC分类号： G06F112
CPC分类号： G11C29/028 , G06F13/1689 , G11C29/02 , G11C29/50012
摘要： A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digital signal is stored in an associated storage circuit and defines a timing offset between the corresponding digital signal and the clock. The clock is output along with each digital signal having the timing offset defined by the corresponding phase command and the digital signals are captured responsive to the clock and evaluated to determine if each digital signal was successfully captured. A phase adjustment command adjusts the value of each phase command. These operations are repeated for a plurality of phase adjustment commands until respective final phase commands allowing all digital signals to be successfully captured is determined and stored in the storage circuits.
摘要翻译：一种用于相对于数字信号相对于时钟输出自适应地调整数字信号的相应定时偏移的方法和电路，以使得锁存器能够接收数字信号以响应于时钟存储信号。每个数字信号的相位指令被存储在相关联的存储电路中，并且定义相应的数字信号和时钟之间的定时偏移。时钟与每个具有由相应相位指令定义的定时偏移的数字信号一起输出，并且响应于时钟捕获数字信号并进行评估以确定每个数字信号是否被成功捕获。相位调整命令调整各相命令的值。对于多个相位调整命令重复这些操作，直到允许成功捕获所有数字信号的各个最终相位命令被确定并存储在存储电路中。

44. 发明授权

US06753675B2 Method and circuit for limiting a pumped voltage 有权
标题翻译：用于限制泵送电压的方法和电路
公开(公告)号：US06753675B2
公开(公告)日：2004-06-22
申请号：US10267278
申请日：2002-10-08
申请人： Ronnie M. Harrison
发明人： Ronnie M. Harrison
IPC分类号： G05F140
CPC分类号： H02M3/073
摘要： A method and circuit control the value of generated voltage derived from a supply voltage as the value of the supply voltage varies, such as during burn-in of an integrated circuit. A voltage generation circuit includes a generator circuit that receives a supply voltage and has a reference node and develops an output voltage from the supply voltage, the output voltage having a value that is a function of a reference voltage applied on the reference node. A coupling circuit receives the supply voltage and operates in response to a voltage control signal to vary an electronic coupling of the supply voltage to the reference node to thereby adjust the value of the reference voltage. A voltage sensing circuit develops the voltage control signal that is applied to the coupling circuit in response to the reference voltage.
摘要翻译：当集成电路的老化期间，电源电压的值变化时，方法和电路控制从电源电压导出的产生电压的值。电压产生电路包括发生器电路，其接收电源电压并具有参考节点并且从所述电源电压产生输出电压，所述输出电压具有作为施加在所述参考节点上的参考电压的函数的值。耦合电路接收电源电压并响应于电压控制信号而操作，以改变电源电压与参考节点的电子耦合，从而调整参考电压的值。电压感测电路响应于参考电压产生施加到耦合电路的电压控制信号。

45. 发明授权

US06744281B2 Method and system for controlling the duty cycle of a clock signal 有权
公开(公告)号：US06744281B2
公开(公告)日：2004-06-01
申请号：US10075517
申请日：2002-02-13
申请人： Ronnie M. Harrison
发明人： Ronnie M. Harrison
IPC分类号： H03K1900
CPC分类号： G06F1/08 , H03K5/1565
摘要： A system for controlling the duty cycle of a clock signal. The system includes a duty cycle adjustment circuit that receives an input clock signal and generates an output clock signal. The duty cycle adjustment circuit charges a capacitor when the input clock signal has a first logic level and discharges the capacitor with the input clock signal has a second logic level. The rates of charge and discharge are controlled by first and second control signals. When the capacitor has been charged to a first transition level, the output clock signal transitions to a first logic level, and when the capacitor has been discharged to a second transition level, the output clock signal transitions to a second logic level. The first and second control signals are supplied by a feedback circuit, which is implemented using an integrator circuit that receives the output clock signal and generates a feedback signal indicative of the duty cycle of the output clock signal. A transconductance amplifier compares the feedback signal to a reference voltage, and generates first and second currents corresponding thereto. These currents are converted to the first and second control signals by a control circuit, which includes a current mirror. The control circuit provides good immunity from power supply fluctuations.

46. 发明授权

US06173432B2 Method and apparatus for generating a sequence of clock signals 失效
标题翻译：用于产生时钟信号序列的方法和装置
公开(公告)号：US06173432B2
公开(公告)日：2001-01-09
申请号：US08879847
申请日：1997-06-20
申请人： Ronnie M. Harrison
发明人： Ronnie M. Harrison
IPC分类号： H03L706
CPC分类号： G11C7/22 , G11C7/1078 , G11C7/109 , G11C7/222 , G11C8/08 , G11C8/10 , G11C11/4076 , G11C11/4093 , H03L7/07 , H03L7/0812 , H03L7/0891
摘要： A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock. As a result, all of the clock signals in the sequence generated by the delay line have respective predetermined phases relative to the phase of the command clock. One of the clock signals in the sequence is selected by a multiplexer to clock a command data latch at a time corresponding to the delay in coupling a command data bit to the latch.
摘要翻译：时钟发生器电路从主时钟信号产生彼此相位相位的时钟信号序列。时钟发生器由内部和外部延迟锁定环形成。内部延迟锁定环路包括电压控制延迟线，其延迟通过多个相应延迟施加到其输入的参考时钟。序列中的两个时钟信号被施加到相位检测器，使得延迟线的输出处的信号相对于彼此具有预定的相位。外部延迟锁定环由电压控制延迟电路形成，该延迟电路通过电压控制延迟延迟命令时钟，以将参考时钟提供给内部延迟锁定环路的延迟线。外延迟锁定环还包括相位检测器，其将命令时钟与由延迟线产生的序列中的一个时钟信号进行比较。外延迟锁定环因此将序列中的一个时钟信号锁定到命令时钟。结果，由延迟线产生的序列中的所有时钟信号相对于命令时钟的相位具有相应的预定相位。序列中的一个时钟信号由多路复用器选择，以在与命令数据位耦合到锁存器的延迟相对应的时间对命令数据锁存器进行时钟。

47. 发明授权

US6119242A Synchronous clock generator including a false lock detector 有权
标题翻译：同步时钟发生器包括一个假锁定检测器
公开(公告)号：US6119242A
公开(公告)日：2000-09-12
申请号：US318293
申请日：1999-05-25
申请人： Ronnie M. Harrison
发明人： Ronnie M. Harrison
IPC分类号： G06F1/06 , G06F1/10 , G11C7/22 , H03L7/07 , H03L7/081 , H03L7/087 , H03L7/089 , H03L7/095 , G06F1/04
CPC分类号： G06F1/06 , G06F1/10 , G11C7/22 , H03L7/07 , H03L7/0812 , H03L7/087 , H03L7/0891 , H03L7/095 , H03L2207/14
摘要： A false lock detector for use in conjunction with a locked loop which produces a plurality of output signals in response to a clock signal is comprised of a logic circuit for receiving first and second signals produced by the locked loop. The logic circuit determines if a predetermined phase relationship exists between the first and second signals and produces an output signal indicative of that determination.
摘要翻译：与用于响应于时钟信号产生多个输出信号的锁定环结合使用的伪锁定检测器包括用于接收由锁定环产生的第一和第二信号的逻辑电路。逻辑电路确定在第一和第二信号之间是否存在预定的相位关系，并产生指示该确定的输出信号。

48. 发明授权

US5920518A Synchronous clock generator including delay-locked loop 失效
标题翻译：同步时钟发生器包括延迟锁定环
公开(公告)号：US5920518A
公开(公告)日：1999-07-06
申请号：US799661
申请日：1997-02-11
申请人： Ronnie M. Harrison , Brent Keeth
发明人： Ronnie M. Harrison , Brent Keeth
IPC分类号： G11C11/407 , G06F1/06 , G11C7/10 , H03L7/00 , H03L7/081
CPC分类号： H03L7/0805 , G11C7/1051 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/222 , H03L7/0812
摘要： A data and command latching circuit includes a delay-locked loop driven by a continuous reference clock signal that generates a delayed output clock signal having a delay controlled by the delay-locked loop. The latching circuit also includes a variable delay circuit external to the delay-locked loop that is driven by a discontinuous reference clock signal. Delay of the external delay circuit is controlled by a control voltage output from the delay-locked loop, so that the delays of the external delay circuit are determined with reference to the continuous reference clock signal. The delayed clock signals from the delay-locked loop activate control data latches to latch control data arriving at the latch circuit. The delayed signals from the variable voltage circuit activate data latches to latch data arriving at the latch circuit.
摘要翻译：数据和命令锁存电路包括由连续参考时钟信号驱动的延迟锁定环路，该延迟锁定环路产生具有由延迟锁定环控制的延迟的延迟输出时钟信号。锁存电路还包括由不连续参考时钟信号驱动的延迟锁定环外部的可变延迟电路。通过从延迟锁定环路输出的控制电压来控制外部延迟电路的延迟，从而参考连续的参考时钟信号确定外部延迟电路的延迟。来自延迟锁定环路的延迟时钟信号激活控制数据锁存器以锁存到达锁存电路的控制数据。来自可变电压电路的延迟信号激活数据锁存器以锁存到达锁存电路的数据。

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