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41. 发明申请

US20130159669A1 LOW LATENCY VARIABLE TRANSFER NETWORK FOR FINE GRAINED PARALLELISM OF VIRTUAL THREADS ACROSS MULTIPLE HARDWARE THREADS 有权
标题翻译：低延迟可变传输网络，用于通过多个硬件线程的虚拟螺纹的精细平行平行
公开(公告)号：US20130159669A1
公开(公告)日：2013-06-20
申请号：US13330831
申请日：2011-12-20
申请人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
发明人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/3824 , G06F9/3828 , G06F9/3851 , G06F9/3891 , G06F9/544 , G06F15/173
摘要： A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.
摘要翻译：一种方法和电路装置利用多核处理器芯片中的多个处理核心的寄存器文件之间的低延迟可变传输网络来支持跨多个硬件线程的虚拟线程的细粒度并行。可变传输网络上的变量的通信可以通过从源处理核心的寄存器文件中的本地寄存器移动到分配给目的地处理核心中的目的地硬件线程的可变寄存器来启动，使得目标硬件线程可以将变量从变量寄存器移动到目标处理核心中的本地寄存器。

42. 发明申请

US20130159668A1 PREDECODE LOGIC FOR AUTOVECTORIZING SCALAR INSTRUCTIONS IN AN INSTRUCTION BUFFER 有权
标题翻译：用于自动执行指令缓冲区中的标准指令的预编码逻辑
公开(公告)号：US20130159668A1
公开(公告)日：2013-06-20
申请号：US13330888
申请日：2011-12-20
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F15/80 , G06F9/302 , G06F9/30
CPC分类号： G06F9/30036 , G06F9/30145 , G06F9/45516 , G06F15/8053
摘要： A circuit arrangement, method, and program product for substituting a plurality of scalar instructions in an instruction stream with a functionally equivalent vector instruction for execution by a vector execution unit. Predecode logic is coupled to an instruction buffer which stores instructions in an instruction stream to be executed by the vector execution unit. The predecode logic analyzes the instructions passing through the instruction buffer to identify a plurality of scalar instructions that may be replaced by a vector instruction in the instruction stream. The predecode logic may generate the functionally equivalent vector instruction based on the plurality of scalar instructions, and the functionally equivalent vector instruction may be substituted into the instruction stream, such that the vector execution unit executes the vector instruction in lieu of the plurality of scalar instructions.
摘要翻译：一种电路装置，方法和程序产品，用于用指令流中的多个标量指令代替由矢量执行单元执行的功能等效的矢量指令。预解码逻辑耦合到指令缓冲器，该指令缓冲器将指令流存储在要由矢量执行单元执行的指令流中。预解码逻辑分析通过指令缓冲器的指令，以识别可由指令流中的向量指令代替的多个标量指令。预解码逻辑可以基于多个标量指令生成功能等效的矢量指令，并且可以将功能等效的矢量指令代入指令流中，使得向量执行单元执行矢量指令来代替多个标量指令。

43. 发明申请

US20130111190A1 OPERATIONAL CODE EXPANSION IN RESPONSE TO SUCCESSIVE TARGET ADDRESS DETECTION 有权
标题翻译：响应终端目标地址检测的操作代码扩展
公开(公告)号：US20130111190A1
公开(公告)日：2013-05-02
申请号：US13287412
申请日：2011-11-02
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/30
CPC分类号： G06F9/30 , G06F9/30145 , G06F9/30181 , G06F9/3832
摘要： A circuit arrangement and method support compression and expansion of instruction opcodes by detecting successive address targeting and decoding a first opcode of an instruction into a second opcode in response to detecting successive address targeting. The circuit arrangement and method execute instructions in an instruction stream and detect successive address targeting by two or more instructions in the instruction stream without the targeted address being utilized as a source address in an instruction executed between the first and second instructions in the instruction stream. Then, based on that detection, the opcode of the second instruction is modified, changed, or appended to such that a different opcode is indicated by the second instruction, such that executing the second instruction causes a different unique type of operation to be performed.
摘要翻译：电路布置和方法通过响应于检测到连续的地址目标来检测连续的地址目标和将指令的第一操作码解码成第二操作码来支持指令操作码的压缩和扩展。电路装置和方法在指令流中执行指令，并且在指令流中的指令流中的第一和第二指令之间执行的指令中，用目标地址作为源地址来检测指令流中两个或多个指令的连续地址定向。然后，基于该检测，第二指令的操作码被修改，改变或附加，使得由第二指令指示不同的操作码，使得执行第二指令导致执行不同的独特类型的操作。

44. 发明授权

US08423749B2 Sequential processing in network on chip nodes by threads generating message containing payload and pointer for nanokernel to access algorithm to be executed on payload in another node 有权
标题翻译：通过线程生成包含有效载荷和纳米核的指针的线程在芯片节点上的顺序处理来访问在另一个节点的有效载荷上执行的算法
公开(公告)号：US08423749B2
公开(公告)日：2013-04-16
申请号：US12255827
申请日：2008-10-22
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/40
CPC分类号： G06F9/54 , H04L45/58
摘要： A computer-implemented method, system and computer program product for controlling an algorithm that is performed on a unit of work in a subsequent software pipeline stage in a Network On a Chip (NOC) is presented. In one embodiment, the method executes a first operation in a first node of the NOC. The first node generates payload, and then loads that payload into a message. The message with the payload is transmitted to a nanokernel that controls a second node in the NOC. The nanokernel calls an algorithm that is needed by a second operation in a second node in the NOC, which uses the algorithm to execute the second operation.
摘要翻译：提出了一种用于控制在片上网络（NOC）中的后续软件流水线阶段中的工作单元上执行的算法的计算机实现的方法，系统和计算机程序产品。在一个实施例中，该方法在NOC的第一节点中执行第一操作。第一个节点生成有效负载，然后将该负载加载到消息中。具有有效载荷的消息被传送到控制NOC中的第二节点的纳米内核。 nanokernel调用NOC中的第二个节点中第二个操作需要的算法，该算法使用该算法来执行第二个操作。

45. 发明授权

US08405670B2 Rolling texture context data structure for maintaining texture data in a multithreaded image processing pipeline 失效
标题翻译：滚动纹理上下文数据结构，用于在多线程图像处理流水线中维护纹理数据
公开(公告)号：US08405670B2
公开(公告)日：2013-03-26
申请号：US12787110
申请日：2010-05-25
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F15/16 , G06F15/80 , G06F13/00 , G06F9/46 , G06F15/00 , G06T1/20 , G06T11/40 , G06K9/54 , G05B19/18 , G05B11/01
CPC分类号： G06T1/20
摘要： A multithreaded rendering software pipeline architecture utilizes a rolling texture context data structure to store multiple texture contexts that are associated with different textures that are being processed in the software pipeline. Each texture context stores state data for a particular texture, and facilitates the access to texture data by multiple, parallel stages in a software pipeline. In addition, texture contexts are capable of being “rolled”, or copied to enable different stages of a rendering pipeline that require different state data for a particular texture to separately access the texture data independently from one another, and without the necessity for stalling the pipeline to ensure synchronization of shared texture data among the stages of the pipeline.
摘要翻译：多线程渲染软件流水线架构使用滚动纹理上下文数据结构来存储与在软件管线中处理的不同纹理相关联的多个纹理上下文。每个纹理上下文存储特定纹理的状态数据，并且便于通过软件流水线中的多个并行级访问纹理数据。此外，纹理上下文能够被滚动或复制以使得需要用于特定纹理的不同状态数据的渲染流水线的不同阶段来独立地彼此独立地访问纹理数据，并且不需要使流水线停止确保在管道的阶段之间共享纹理数据的同步。

46. 发明申请

US20120209944A1 Software Pipelining On A Network On Chip 有权
标题翻译：网络芯片上的软件流水线
公开(公告)号：US20120209944A1
公开(公告)日：2012-08-16
申请号：US13453380
申请日：2012-04-23
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F15/167
CPC分类号： H04L49/15 , H04L49/109 , H04L49/252 , H04L49/3036 , H04L49/90 , H04L49/901
摘要： Memory sharing in a software pipeline on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, including segmenting a computer software application into stages of a software pipeline, the software pipeline comprising one or more paths of execution; allocating memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated; determining, in dependence upon the data elements for determining when the shared memory can be deallocated, that the shared memory can be deallocated; and deallocating the shared memory.
摘要翻译：在芯片上的软件管道（“NOC”）中的内存共享，NOC包括集成处理器（IP）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和网络接口控制器，其中每个存储器通信控制器控制IP块和存储器之间的通信以及控制通过路由器进行IP间块通信的每个网络接口控制器，包括将计算机软件应用程序分解成软件流水线的阶段，所述软件流水线包括一个或多个执行路径; 在至少两个阶段中分配要共享的存储器，包括创建智能指针，所述智能指针包括用于确定何时可以释放所述共享存储器的数据元素; 根据用于确定何时可以释放共享存储器的数据元素确定可以释放共享存储器; 并释放共享内存。

47. 发明申请

US20120179899A1 UPGRADEABLE PROCESSOR ENABLING HARDWARE LICENSING 审中-公开
标题翻译：可升级处理器启用硬件许可
公开(公告)号：US20120179899A1
公开(公告)日：2012-07-12
申请号：US12986660
申请日：2011-01-07
申请人： Paul E. Schardt , Robert A. Shearer
发明人： Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F9/00
CPC分类号： G06F17/5027 , G06F17/5054
摘要： A technique for programming a configurable co-processor in a processing system is disclosed. The configurable co-processor includes field programmable logic and is configured using a pre-generated co-processor image. The technique involves enabling a user application to program the configurable co-processor with certain application-specific hardware based processing functions. One advantage of the present invention is that application-specific hardware design optimizations may be implemented to improve application performance after hardware for the processing system has been manufactured.
摘要翻译：公开了一种用于在处理系统中编程可配置协处理器的技术。可配置的协处理器包括现场可编程逻辑，并且使用预先生成的协处理器映像进行配置。该技术涉及使得用户应用程序能够使用特定的基于特定于硬件的处理功能对可配置协处理器进行编程。本发明的一个优点是，可以实现特定于应用的硬件设计优化，以在制造用于处理系统的硬件之后提高应用性能。

48. 发明申请

US20110320771A1 INSTRUCTION UNIT WITH INSTRUCTION BUFFER PIPELINE BYPASS 有权
标题翻译：指令单元与指令缓冲管道旁路
公开(公告)号：US20110320771A1
公开(公告)日：2011-12-29
申请号：US12824812
申请日：2010-06-28
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/38 , G06F9/312 , G06F12/08
CPC分类号： G06F9/3814 , G06F9/3861 , G06F12/0853 , G06F2205/065
摘要： A circuit arrangement and method selectively bypass an instruction buffer for selected instructions so that bypassed instructions can be dispatched without having to first pass through the instruction buffer. Thus, for example, in the case that an instruction buffer is partially or completely flushed as a result of an instruction redirect (e.g., due to a branch mispredict), instructions can be forwarded to subsequent stages in an instruction unit and/or to one or more execution units without the latency associated with passing through the instruction buffer.
摘要翻译：电路装置和方法选择性地旁路用于所选指令的指令缓冲器，使得可以调度旁路指令而不必首先通过指令缓冲器。因此，例如，在指令重定向（例如，由于分支错误预测）导致指令缓冲器被部分或全部冲洗的情况下，可以将指令转发到指令单元中的后续阶段和/或向一个或更多的执行单元，而没有与通过指令缓冲器相关联的延迟。

49. 发明申请

US20110320724A1 DMA-BASED ACCELERATION OF COMMAND PUSH BUFFER BETWEEN HOST AND TARGET DEVICES 失效
标题翻译：基于DMA的主机和目标设备之间的命令推挽缓存的加速
公开(公告)号：US20110320724A1
公开(公告)日：2011-12-29
申请号：US12824674
申请日：2010-06-28
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F12/08
CPC分类号： G06F13/28
摘要： Direct Memory Access (DMA) is used in connection with passing commands between a host device and a target device coupled via a push buffer. Commands passed to a push buffer by a host device may be accumulated by the host device prior to forwarding the commands to the push buffer, such that DMA may be used to collectively pass a block of commands to the push buffer. In addition, a host device may utilize DMA to pass command parameters for commands to a command buffer that is accessible by the target device but is separate from the push buffer, with the commands that are passed to the push buffer including pointers to the associated command parameters in the command buffer.
摘要翻译：直接存储器访问（DMA）用于在通过推送缓冲器耦合的主机设备和目标设备之间传递命令。由宿主设备传递到推送缓冲器的命令可以在将命令转发到推送缓冲器之前被主机设备累积，使得可以使用DMA来共同地将一组命令传递给推送缓冲器。此外，主机设备可以利用DMA将用于命令的命令参数传递给目标设备可访问但与推送缓冲区分离的命令缓冲区，其中传递到推送缓冲器的命令包括指向相关命令的指针命令缓冲区中的参数。

50. 发明申请

US20110317712A1 Recovering Data From A Plurality of Packets 失效
标题翻译：从多个数据包恢复数据
公开(公告)号：US20110317712A1
公开(公告)日：2011-12-29
申请号：US12823689
申请日：2010-06-25
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： H04L12/56 , G06F11/00
CPC分类号： H04L49/9047
摘要： A method includes receiving a plurality of packets at an integrated processor block of a network on a chip device. The plurality of packets includes a first packet that includes an indication of a start of data associated with a pixel shader application. The method includes recovering the data from the plurality of packets. The method also includes storing the recovered data in a dedicated packet collection memory within the network on the chip device. The method further includes retaining the data stored in the dedicated packet collection memory during an interruption event. Upon completion of the interruption event, the method includes copying packets stored in the dedicated packet collection memory prior to the interruption event to an inbox of the network on the chip device for processing.
摘要翻译：一种方法包括在芯片设备上的网络的集成处理器块处接收多个分组。多个分组包括包括与像素着色器应用相关联的数据开始的指示的第一分组。该方法包括从多个分组中恢复数据。该方法还包括将恢复的数据存储在芯片设备上的网络内的专用分组收集存储器中。该方法还包括在中断事件期间保留存储在专用分组收集存储器中的数据。在中断事件完成时，该方法包括在中断事件之前将存储在专用分组收集存储器中的分组复制到芯片装置上的网络的收件箱进行处理。

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