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41. 发明申请

US20130106496A1 NANOWIRE EFUSES 有权
公开(公告)号：US20130106496A1
公开(公告)日：2013-05-02
申请号：US13611081
申请日：2012-09-12
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01H37/76
CPC分类号： H01L29/785 , H01H2085/0283 , H01H2300/036 , H01L23/5256 , H01L29/0673 , H01L29/42392 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuses and methods for forming the same are shown that include forming a wire between a first pad and a second pad on a substrate, forming a blocking structure around a portion of the wire, and depositing a metal layer on the wire and first and second pads to form a metal compound, wherein the metal compound fully penetrates the portion of the wire within the blocking structure.

42. 发明授权

US08404539B2 Self-aligned contacts in carbon devices 有权
标题翻译：碳装置中的自对准触点
公开(公告)号：US08404539B2
公开(公告)日：2013-03-26
申请号：US12832224
申请日：2010-07-08
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L21/8238
CPC分类号： H01L29/1606 , B82Y10/00 , H01L29/165 , H01L29/41733 , H01L29/41766 , H01L29/41775 , H01L29/66431 , H01L29/66742 , H01L29/7781 , H01L29/78 , H01L29/78684 , H01L51/0048
摘要： A method for forming a semiconductor device includes forming a carbon material on a substrate, forming a gate stack on the carbon material, removing a portion of the substrate to form at least one cavity defined by a portion of the carbon material and the substrate, and forming a conductive contact in the at least one cavity.
摘要翻译：一种用于形成半导体器件的方法包括在基片上形成碳材料，在碳材料上形成栅叠层，去除基片的一部分以形成由碳材料和基片的一部分限定的至少一个空腔，以及在所述至少一个空腔中形成导电接触。

43. 发明授权

US08384065B2 Gate-all-around nanowire field effect transistors 有权
标题翻译：栅极全能纳米线场效应晶体管
公开(公告)号：US08384065B2
公开(公告)日：2013-02-26
申请号：US12631199
申请日：2009-12-04
申请人： Sarunya Bangsaruntip , Josephine B. Chang , Guy M. Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Josephine B. Chang , Guy M. Cohen , Jeffrey W. Sleight
IPC分类号： H01L29/66
CPC分类号： H01L29/66772 , B82Y10/00 , H01L21/845 , H01L27/1211 , H01L29/0665 , H01L29/42392 , H01L29/66439 , H01L29/66628 , H01L29/775 , H01L29/78696
摘要： A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region.
摘要翻译：一种用于形成纳米线场效应晶体管（FET）器件的方法，该方法包括在半导体衬底上形成悬浮的纳米线，在纳米线的一部分周围形成栅极结构，形成邻近栅极的侧壁和周围部分的保护隔离层的纳米线从栅极延伸，去除未被间隔物结构保护的纳米线的暴露部分，以及在纳米线的暴露的横截面上外延生长掺杂的半导体材料，以形成源极区域和漏极区域。

44. 发明授权

US08378429B2 Selective floating body SRAM cell 有权
标题翻译：选择性浮体SRAM单元
公开(公告)号：US08378429B2
公开(公告)日：2013-02-19
申请号：US13045784
申请日：2011-03-11
申请人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Steven J. Koester , Jeffrey W. Sleight
IPC分类号： H01L21/70
CPC分类号： H01L27/088 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/1207 , H01L27/1211 , H01L29/7841
摘要： A memory cell has N≧16 transistors, in which two are access transistors, at least one pair [say (N-2)/2] are pull-up transistors, and at least another pair [say (N-2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.
摘要翻译：存储单元具有N≥16个晶体管，其中两个是存取晶体管，至少一对[例如（N-2）/ 2]是上拉晶体管，并且至少另一对[例如（N-2）/ 2 ]是下拉晶体管。上拉和下拉晶体管都耦合在两个存取晶体管之间。每个存取晶体管和上拉晶体管是相同类型的，p型或n型。每个下拉晶体管是另一种类型的p型或n型。存取晶体管是浮体装置。下拉晶体管是非浮体器件。上拉晶体管可以是浮动或非浮动体器件。还详细描述了制造存储器单元的各种具体实施方式和方法。

45. 发明授权

US08362568B2 Recessed contact for multi-gate FET optimizing series resistance 有权
标题翻译：嵌入式多栅极FET优化串联电阻
公开(公告)号：US08362568B2
公开(公告)日：2013-01-29
申请号：US12583933
申请日：2009-08-28
申请人： Chung-Hsun Lin , Josephine B. Chang
发明人： Chung-Hsun Lin , Josephine B. Chang
IPC分类号： H01L29/94
CPC分类号： H01L29/66795 , H01L29/66636 , H01L29/785
摘要： A transistor, which can be referred to as a multi-gate transistor or as a FinFET, includes a gate structure having a length, a width and a height. The transistor further includes at least one electrically conductive channel or fin between a source region and a drain region that passes through the width of the gate structure. The channel has a first height (h1) within the gate structure that is less than the height of the gate structure, and has a second height (h2) external to the gate structure, where h2 is less than h1. The transistor further includes a silicide layer disposed at least partially over the at least one channel external to the gate structure. Reducing the fin height external to the gate structure is shown to beneficially reduce parasitic resistance.
摘要翻译：可以称为多栅极晶体管或FinFET的晶体管包括具有长度，宽度和高度的栅极结构。晶体管还包括通过栅极结构的宽度的源极区域和漏极区域之间的至少一个导电沟道或鳍。通道在门结构内具有小于栅极结构的高度的第一高度（h1），并且具有栅极结构外部的第二高度（h2），其中h2小于h1。晶体管还包括至少部分地设置在栅极结构外部的至少一个沟道上的硅化物层。降低栅极结构外部的翅片高度被显示有利地减少寄生电阻。

46. 发明申请

US20120326236A1 MULTI-GATE TRANSISTOR HAVING SIDEWALL CONTACTS 有权
标题翻译：具有端子接触器的多栅极晶体管
公开(公告)号：US20120326236A1
公开(公告)日：2012-12-27
申请号：US13604340
申请日：2012-09-05
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66795 , H01L2029/7858
摘要： A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.
摘要翻译：一种具有多个侧壁触点的多栅极晶体管及其制造方法，包括在半导体衬底上形成半导体鳍片并蚀刻半导体鳍片内的沟槽，在蚀刻沟槽内沉积氧化物材料，并蚀刻氧化物材料以形成沿着蚀刻沟槽内的暴露壁的虚拟氧化物层; 以及沿所述虚拟氧化物层的垂直侧壁形成间隔电介质层。该方法还包括去除半导体鳍片中的沟道区域中的暴露的虚拟氧化物层并且在间隔物电介质层下方形成沿着半导体鳍片中的沟道区域的侧壁形成高k材料衬垫，在蚀刻沟槽，并且在半导体鳍片内沿虚拟氧化物层的相邻侧壁形成多个侧壁接触。

47. 发明申请

US20120306000A1 Formation of Field Effect Transistor Devices 审中-公开
标题翻译：场效应晶体管器件的形成
公开(公告)号：US20120306000A1
公开(公告)日：2012-12-06
申请号：US13118689
申请日：2011-05-31
申请人： Josephine B. Chang , Paul C. Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul C. Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/0207 , H01L29/66545
摘要： A method includes defining active regions on a substrate, forming a dummy gate stack material over exposed portions of the active regions of the substrate and non-active regions of the substrate, removing portions of the dummy gate stack material to expose portions of the active regions and non-active regions of the substrate and define dummy gate stacks, forming a gap-fill dielectric material over the exposed portions of the substrate and the source and drain regions, removing portions of the gap-fill dielectric material to expose the dummy gate stacks, removing the dummy gate stacks to form dummy gate trenches, forming dividers within the dummy gate trenches, depositing gate stack material inside the dummy gate trenches, over the dividers, and the gap-fill dielectric material, and removing portions of the gate stack material to define gate stacks.
摘要翻译：一种方法包括在衬底上限定有源区域，在衬底的有源区域和衬底的非有源区域的暴露部分上形成虚拟栅极堆叠材料，去除虚拟栅极堆叠材料的部分以暴露部分有源区域和非活性区域，并且限定伪栅极堆叠，在衬底和源极和漏极区域的暴露部分上形成间隙填充电介质材料，去除间隙填充电介质材料的部分以暴露伪栅极堆叠，去除虚拟栅极堆叠以形成伪栅极沟槽，在虚拟栅极沟槽内形成分隔线，在虚拟栅极沟槽内部，在分隔器上方形成栅极堆叠材料，以及间隙填充电介质材料，以及去除栅极堆叠材料的部分定义栅极堆叠。

48. 发明申请

US20120292597A1 Self-Aligned Contacts in Carbon Devices 有权
标题翻译：碳装置中的自对准触点
公开(公告)号：US20120292597A1
公开(公告)日：2012-11-22
申请号：US13562827
申请日：2012-07-31
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L29/775
CPC分类号： H01L29/1606 , B82Y10/00 , H01L29/165 , H01L29/41733 , H01L29/41766 , H01L29/41775 , H01L29/66431 , H01L29/66742 , H01L29/7781 , H01L29/78 , H01L29/78684 , H01L51/0048
摘要： A semiconductor device includes a carbon layer disposed on a substrate, a gate stack disposed on a portion of the carbon layer, a first cavity defined by the carbon layer and the substrate, a second cavity defined by the carbon layer and the substrate, a source region including a first conductive contact disposed in the first cavity, a drain region including a second conductive contact disposed in the second cavity.
摘要翻译：半导体器件包括设置在基底上的碳层，设置在碳层的一部分上的栅极叠层，由碳层和衬底限定的第一腔，由碳层和衬底限定的第二腔，源区域，包括设置在第一腔中的第一导电触点，漏区，包括设置在第二腔中的第二导电触点。

49. 发明申请

US20120286377A1 Nanoelectromechanical Structures Exhibiting Tensile Stress And Techniques For Fabrication Thereof 审中-公开
标题翻译：展示拉伸应力的纳米机电结构及其制造技术
公开(公告)号：US20120286377A1
公开(公告)日：2012-11-15
申请号：US13103193
申请日：2011-05-09
申请人： Josephine B. Chang , Sebastian U. Engelmann , Michael A. Guillorn , Fei Liu , Conal E. Murray
发明人： Josephine B. Chang , Sebastian U. Engelmann , Michael A. Guillorn , Fei Liu , Conal E. Murray
IPC分类号： H01L29/84 , H01L21/3105 , H01L29/06
CPC分类号： H01L29/84 , B81B3/0072 , B81B2203/0109 , B81B2203/0307 , H01L29/0673
摘要： Improved nano-electromechanical system devices and structures and systems and techniques for their fabrication. In one embodiment, a structure comprises an underlying substrate separated from first and second anchor points by first and second insulating support points, respectively. The first and second anchor points are joined by a beam. First and second deposition regions overlie the first and second anchor points, respectively, and the first and second deposition regions exert compression on the first and second anchor points, respectively. The compression on the first and second anchor points causes opposing forces on the beam, subjecting the beam to a tensile stress. The first and second deposition regions suitably exhibit an internal tensile stress having an achievable maximum varying with their thickness, so that the tensile stress exerted on the beam depends at least on part on the thickness of the first and second deposition regions.
摘要翻译：改进的纳米机电系统设备及其制造的结构及系统和技术。在一个实施例中，结构包括分别通过第一和第二绝缘支撑点从第一和第二锚定点分离的下面的基底。第一和第二锚定点通过梁连接。第一和第二沉积区域分别覆盖在第一和第二锚定点上，并且第一和第二沉积区域分别在第一和第二锚定点上施加压缩。第一和第二锚固点上的压缩在梁上产生相反的力，使梁受到拉伸应力。第一和第二沉积区域适当地呈现具有随其厚度变化的可实现最大值的内部拉伸应力，使得施加在梁上的拉伸应力至少部分地取决于第一和第二沉积区域的厚度。

50. 发明授权

US08242485B2 Source/drain technology for the carbon nano-tube/graphene CMOS with a single self-aligned metal silicide process 有权
标题翻译：碳纳米管/石墨烯CMOS的源/漏技术，采用单独的自对准金属硅化物工艺
公开(公告)号：US08242485B2
公开(公告)日：2012-08-14
申请号：US12762832
申请日：2010-04-19
申请人： Josephine B. Chang , Christian Lavoie , Zhen Zhang
发明人： Josephine B. Chang , Christian Lavoie , Zhen Zhang
IPC分类号： H01L29/06 , H01L21/44
CPC分类号： H01L29/1606 , B82Y10/00 , H01L29/0665 , H01L29/45 , H01L29/66628 , H01L29/66742 , H01L29/775 , H01L29/7781 , H01L29/78618 , H01L29/78684 , H01L51/0048 , H01L51/105
摘要： Electronic devices having carbon-based materials and techniques for making contact to carbon-based materials in electronic devices are provided. In one aspect, a device is provided having a carbon-based material; and at least one electrical contact to the carbon-based material comprising a metal silicide, germanide or germanosilicide. The carbon-based material can include graphene or carbon nano-tubes. The device can further include a segregation region, having an impurity, separating the carbon-based material from the metal silicide, germanide or germanosilicide, wherein the impurity has a work function that is different from a work function of the metal silicide, germanide or germanosilicide. A method for fabricating the device is also provided.
摘要翻译：提供了具有碳基材料的电子器件和用于与电子器件中的碳基材料接触的技术。一方面，提供一种具有碳基材料的装置; 以及与包含金属硅化物，锗化锗或锗硅化物的碳基材料的至少一个电接触。碳基材料可以包括石墨烯或碳纳米管。该装置还可以包括具有杂质的偏析区域，从金属硅化物，锗化锗或锗硅化物中分离碳基材料，其中杂质具有不同于金属硅化物，锗化锗或锗硅酸盐的功函数。还提供了一种用于制造该装置的方法。

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