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41. 发明申请

US20130102151A1 METHODS OF MANUFACTURING NAND FLASH MEMORY DEVICES 有权
标题翻译：制造NAND闪存存储器件的方法
公开(公告)号：US20130102151A1
公开(公告)日：2013-04-25
申请号：US13709131
申请日：2012-12-10
申请人： Jang-ho Park , Jae-kwan Park , Dong-hwa Kwak , So-wi Jin , Byung-jun Hwang , Nam-su Lim
发明人： Jang-ho Park , Jae-kwan Park , Dong-hwa Kwak , So-wi Jin , Byung-jun Hwang , Nam-su Lim
IPC分类号： H01L21/02
CPC分类号： H01L23/48 , G11C5/063 , G11C16/0483 , H01L21/02697 , H01L21/0337 , H01L21/32139 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction
摘要翻译： NAND闪速存储器件包括布置在多层衬底的公共层上的多个连续导体，所述多个连续导体包括沿着第一方向平行延伸的相应的导线，设置在相应导电线的端部处的相应接触焊盘和相应的导电虚拟线沿着第二方向从接触焊盘平行延伸

42. 发明申请

US20120082367A1 METHOD OF FORMING IMAGE OF SEMICONDUCTOR DEVICE, AND METHOD OF DETECTING A DEFECT OF THE SEMICONDUCTOR DEVICE BY USING THE IMAGE FORMING METHOD 审中-公开
标题翻译：形成半导体器件的图像的方法以及通过使用图像形成方法检测半导体器件的缺陷的方法
公开(公告)号：US20120082367A1
公开(公告)日：2012-04-05
申请号：US13237993
申请日：2011-09-21
申请人： Jung-hoon Byun , Yong-min Cho , Soo-bok Chin , Jae-kwan Park , Seok-woo Nam , Tae-yong Lee , Kee-Hong Lee , Young-min Kim
发明人： Jung-hoon Byun , Yong-min Cho , Soo-bok Chin , Jae-kwan Park , Seok-woo Nam , Tae-yong Lee , Kee-Hong Lee , Young-min Kim
IPC分类号： G06K9/48 , G06K9/00 , G06K9/36
CPC分类号： G06T7/0002 , G06T2207/10016 , G06T2207/10061 , G06T2207/30148 , G06T2207/30168
摘要： A method forms an ultimate or final image of a sample by selecting some of a plurality of image frames and integrating the selected frames. The method includes providing a semiconductor device including a region of interest and a peripheral region; obtaining a plurality of image frames each including a region of interest image and a peripheral region image respectively corresponding to the region of interest and the peripheral region; selecting at least some of the plurality of image frames based on a contrast between the region of interest image and the peripheral region image; and obtaining an image of the semiconductor device by integrating the selected image frames.
摘要翻译：方法通过选择多个图像帧中的一些并且对所选择的帧进行积分来形成样本的最终或最终图像。该方法包括提供包括感兴趣区域和周边区域的半导体器件; 获得各自包括分别对应于感兴趣区域和周边区域的感兴趣区域图像和周边区域图像的多个图像帧; 基于感兴趣区域与外围区域图像之间的对比度来选择多个图像帧中的至少一些; 以及通过对所选择的图像帧进行积分来获得半导体器件的图像。

43. 发明申请

US20110211392A1 CELL STRING OF A MEMORY CELL ARRAY AND METHOD OF ERASING THE SAME 审中-公开
标题翻译：存储单元阵列的单元格字符串及其擦除方法
公开(公告)号：US20110211392A1
公开(公告)日：2011-09-01
申请号：US12961647
申请日：2010-12-07
申请人： Jae-Ho Kim , Jae-Kwan Park , Byung-Jun Hwang , Sung-Bo Shim , Hye-Young Kwon
发明人： Jae-Ho Kim , Jae-Kwan Park , Byung-Jun Hwang , Sung-Bo Shim , Hye-Young Kwon
IPC分类号： G11C16/06 , H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： G11C16/16 , G11C16/0408 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A cell string included in a memory cell array of a nonvolatile memory device includes a plurality of memory cells, a string select transistor, and a ground select transistor. The plurality of memory cells are connected in series. The string select transistor is connected between a bitline and the plurality of memory cells, and has a structure substantially the same as a structure of each memory cell. The ground select transistor is connected between the plurality of memory cells and a common source line, and has a structure substantially the same as the structure of each memory cell.
摘要翻译：包括在非易失性存储器件的存储单元阵列中的单元串包括多个存储单元，串选择晶体管和接地选择晶体管。多个存储单元串联连接。串选择晶体管连接在位线和多个存储单元之间，并且具有与每个存储单元的结构基本相同的结构。接地选择晶体管连接在多个存储单元和公共源极线之间，并且具有与每个存储单元的结构基本相同的结构。

44. 发明授权

US07842571B2 Method for forming semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US07842571B2
公开(公告)日：2010-11-30
申请号：US11623269
申请日：2007-01-15
申请人： Dong-Hwa Kwak , Jae-Kwan Park , Jae-Hwang Sim , Jin-Ho Kim , Ki-Nam Kim
发明人： Dong-Hwa Kwak , Jae-Kwan Park , Jae-Hwang Sim , Jin-Ho Kim , Ki-Nam Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/76897 , H01L21/76816 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： In one embodiment a semiconductor device includes odd contacts and respective odd lines. Spacers are formed on sidewalls of the odd lines and even openings for even lines are formed by performing an etching process. Even contacts are formed in the even openings and then even lines are formed.
摘要翻译：在一个实施例中，半导体器件包括奇数触点和相应的奇数行。间隔物形成在奇数行的侧壁上，并且通过执行蚀刻工艺形成均匀线的均匀开口。偶数触点形成在均匀开口中，然后形成均匀的线。

45. 发明授权

US07772069B2 Methods of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US07772069B2
公开(公告)日：2010-08-10
申请号：US12074992
申请日：2008-03-07
申请人： Sang-Yong Park , Sung-Hyun Kwon , Jae-Hwang Sim , Keon-Soo Kim , Jae-Kwan Park
发明人： Sang-Yong Park , Sung-Hyun Kwon , Jae-Hwang Sim , Keon-Soo Kim , Jae-Kwan Park
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/0334 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/11524 , H01L27/11568
摘要： A method of forming a semiconductor device is provided. A plurality of first guide patterns are formed on a substrate. A mask layer is conformally formed on the substrate. Second guide patterns are formed in empty regions on respective sides of the first guide patterns. The mask layer is planarized and the first and second guide patterns are removed. The mask layer is etched by an anisotropic etching process.
摘要翻译：提供一种形成半导体器件的方法。多个第一引导图案形成在基板上。掩模层在基底上共形地形成。第二引导图案形成在第一引导图案的相应侧上的空白区域中。掩模层被平坦化，并且去除第一和第二引导图案。通过各向异性蚀刻工艺蚀刻掩模层。

46. 发明授权

US07626228B2 NAND-type non-volatile memory devices having a stacked structure 失效
标题翻译：具有堆叠结构的NAND型非易失性存储器件
公开(公告)号：US07626228B2
公开(公告)日：2009-12-01
申请号：US11637686
申请日：2006-12-12
申请人： Jae-Kwan Park , Ki-Nam Kim , Soon-Moon Jung
发明人： Jae-Kwan Park , Ki-Nam Kim , Soon-Moon Jung
IPC分类号： H01L29/792 , H01L23/48 , H01L23/52
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11568 , H01L27/11578
摘要： A NAND-type nonvolatile memory device includes a semiconductor substrate and a first ground selection line and a first string selection line disposed on the substrate in parallel to each other. A plurality of parallel first word lines are interposed on the substrate between the first ground selection line and the first string selection line. A first impurity-doped region is formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line. A first interlayer dielectric layer is disposed on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate. An epitaxial contact plug contacts the semiconductor substrate through the first interlayer dielectric layer. A single crystalline semiconductor layer is disposed on the first interlayer dielectric layer that contacts the epitaxial contact plug. A plurality of parallel second word lines is disposed on the single crystalline semiconductor layer. A second impurity-doped region formed in the single crystalline semiconductor layer adjacent to the second word lines. A second interlayer dielectric layer is disposed on the plurality of second word lines and the single crystalline semiconductor layer.
摘要翻译： NAND型非易失性存储器件包括半导体衬底和彼此平行地布置在衬底上的第一接地选择线和第一串选择线。在第一接地选择线和第一串选择线之间的基板上插入多个平行的第一字线。在与第一字线，第一地选择线和第一串选择线相邻的半导体衬底中形成第一杂质掺杂区。第一层间介电层设置在第一接地选择线，第一串选择线，多个第一字线和半导体衬底上。外延接触插塞通过第一层间介电层与半导体衬底接触。单晶半导体层设置在与外延接触插塞接触的第一层间电介质层上。多个平行的第二字线布置在单晶半导体层上。形成在与第二字线相邻的单晶半导体层中的第二杂质掺杂区。第二层间介电层设置在多个第二字线和单晶半导体层上。

47. 发明申请

US20090286404A1 Method of forming minute patterns in semiconductor device using double patterning 有权
标题翻译：使用双重图案化在半导体器件中形成微小图案的方法
公开(公告)号：US20090286404A1
公开(公告)日：2009-11-19
申请号：US12453307
申请日：2009-05-06
申请人： Sang-yong Park , Jae-kwan Park , Yong-sik Yim , Jae-Hwang Sim
发明人： Sang-yong Park , Jae-kwan Park , Yong-sik Yim , Jae-Hwang Sim
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32139
摘要： A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.
摘要翻译：更具体地，涉及一种在半导体器件中形成微小图案的方法，更具体地，涉及通过双重图案形成在基底图案之间具有偶数个插入图案的半导体器件中的微小图案的方法，包括在第一基本图案和第二基底图案之间的插入图案在半导体基板上横向分离的图案，其中交替地重复第一插入图案和第二插入图案以形成插入图案，该方法包括对与第二插入图案相邻的第二插入图案进行部分蚀刻的操作第二基本图案或形成屏蔽层图案的操作，从而形成偶数个插入图案。

48. 发明申请

US20080057644A1 Semiconductor devices having a convex active region and methods of forming the same 有权
标题翻译：具有凸起的有源区的半导体器件及其形成方法
公开(公告)号：US20080057644A1
公开(公告)日：2008-03-06
申请号：US11642198
申请日：2006-12-20
申请人： Dong-Hwa Kwak , Jae-Kwan Park , Yong-Sik Yim , Won-Cheol Jeong , Jae-Hwang Sim
发明人： Dong-Hwa Kwak , Jae-Kwan Park , Yong-Sik Yim , Won-Cheol Jeong , Jae-Hwang Sim
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L21/76224 , H01L21/823431 , H01L21/823481 , H01L27/11568 , H01L27/11573 , H01L29/66795 , H01L29/7853 , H01L29/7854
摘要： Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.
摘要翻译：形成半导体器件的方法包括在具有有源区和器件隔离区的半导体衬底上形成沟槽掩模图案。使用沟槽掩模图案作为扩散掩模进行热氧化处理，以形成限定有源区的凸上表面的热氧化层。使用沟槽掩模图案作为蚀刻掩模蚀刻热氧化物层和半导体衬底，以形成限定有源区的凸上表面的沟槽。去除沟槽掩模图案以露出活性区域的凸上表面。形成在有源区域上延伸的栅极图案。

49. 发明申请

US20060152262A1 Pulse generators with variable pulse width and sense amplifiers using the same and related methods 审中-公开
标题翻译：具有可变脉冲宽度的脉冲发生器和使用相同方法的读出放大器
公开(公告)号：US20060152262A1
公开(公告)日：2006-07-13
申请号：US11327681
申请日：2006-01-06
申请人： Jae-Kwan Park
发明人： Jae-Kwan Park
IPC分类号： H03K3/017
CPC分类号： H03K5/133 , G11C7/08 , H03K5/153 , H03K2005/00032 , H03K2005/00202
摘要： Pulse generators include a delay circuit that is responsive to an input signal. The pulse generators also include an output circuit that is configured to generate an output pulse signal in response to the output of the delay circuit. In these pulse generators, the delay circuit has a variable delay that increases proportional to increases in a power supply voltage. Sense amplifiers that include these pulse generators are also provided.
摘要翻译：脉冲发生器包括响应于输入信号的延迟电路。脉冲发生器还包括输出电路，其配置为响应于延迟电路的输出而产生输出脉冲信号。在这些脉冲发生器中，延迟电路具有与电源电压增加成比例的可变延迟。还提供了包括这些脉冲发生器的感应放大器。

50. 发明授权

US06248636B1 Method for forming contact holes of semiconductor memory device 失效
标题翻译：形成半导体存储器件接触孔的方法
公开(公告)号：US06248636B1
公开(公告)日：2001-06-19
申请号：US09086762
申请日：1998-05-28
申请人： Jae-kwan Park
发明人： Jae-kwan Park
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76802
摘要： A novel method for forming contact holes is disclosed. According to the present invention, a silicon substrate is prevented from being over-etched by performing a two-step etching process. The first step is to etch a thick interlayer insulating layer until a thin etch stopper layer, formed beneath the interlayer insulating layer, is exposed. The second step is to over-etch the thin etch stopper layer. With this method, a lower capacitor electrode or a bit line can be prevented from being short-circuited with a well region of the silicon substrate, thereby reducing leakage currents.
摘要翻译：公开了一种用于形成接触孔的新方法。根据本发明，通过进行两步蚀刻处理来防止硅衬底被过度蚀刻。第一步是蚀刻厚的层间绝缘层，直到形成在层间绝缘层下面的薄的蚀刻停止层被暴露。第二步是过蚀刻薄蚀刻停止层。利用这种方法，可以防止下电容器电极或位线与硅衬底的阱区短路，从而减少漏电流。

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