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41. 发明授权

US5430854A Simd with selective idling of individual processors based on stored conditional flags, and with consensus among all flags used for conditional branching 失效
标题翻译： Simd根据存储的条件标志对各个处理器进行选择性空闲，并在所有用于条件分支的标志之间保持一致
公开(公告)号：US5430854A
公开(公告)日：1995-07-04
申请号：US144219
申请日：1993-10-27
申请人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Michael Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
发明人： David L. Sprague , Kevin Harney , Eiichi Kowashi , Michael Keith , Allen H. Simon , Michael Papadopoulos , Walter P. Hays , George F. Salem , Shih-Wei Shiue , Anthony P. Bertapelli , Vitaly H. Shilman
IPC分类号： G06F12/08 , G06F9/30 , G06F9/38 , G06F15/80 , G06T1/20
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30149 , G06F9/3802 , G06F9/3863
摘要： A data processing system having execution units for executing instruction sequences determines at least two conditionals in accordance with the instructions and sets respective flags according to the determined conditionals. These flags are stored and later retrieved sequentially and the execution unit executes selected instructions of the instruction sequence according to the sequentially retrieved mask flags. These masked flags may be stored sequentially in a stack for sequential retrieval at a later time.
摘要翻译：具有用于执行指令序列的执行单元的数据处理系统根据指令确定至少两个条件，并根据确定的条件设置相应的标志。这些标志被依次存储和稍后检索，并且执行单元根据顺序检索的掩码标志来执行指令序列的所选择的指令。这些屏蔽的标志可以顺序地存储在堆栈中，以便在稍后的时间进行顺序检索。

42. 发明授权

US08725787B2 Processor for performing multiply-add operations on packed data 失效
公开(公告)号：US08725787B2
公开(公告)日：2014-05-13
申请号：US13456761
申请日：2012-04-26
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

43. 发明申请

US20130198254A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 有权
公开(公告)号：US20130198254A1
公开(公告)日：2013-08-01
申请号：US13801356
申请日：2013-03-13
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
IPC分类号： G06F17/10
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

44. 发明授权

US07395298B2 Method and apparatus for performing multiply-add operations on packed data 失效
标题翻译：对打包数据执行多重加法运算的方法和装置
公开(公告)号：US07395298B2
公开(公告)日：2008-07-01
申请号：US10611621
申请日：2003-06-30
申请人： Eric Debes , William W. Macy , Jonathan J. Tyler , Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Eric Debes , William W. Macy , Jonathan J. Tyler , Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/5324 , G06F7/4812 , G06F7/49921 , G06F7/5338 , G06F7/5443 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3885 , G06F15/7857 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

45. 发明授权

US06470370B2 Method and apparatus for multiplying and accumulating complex numbers in a digital filter 有权
标题翻译：用于在数字滤波器中乘法和累加复数的方法和装置
公开(公告)号：US06470370B2
公开(公告)日：2002-10-22
申请号：US09760969
申请日：2001-01-16
申请人： Stephen A. Fischer , Larry M. Mennemeier , Alexander D. Peleg , Carole Dulong , Eiichi Kowashi
发明人： Stephen A. Fischer , Larry M. Mennemeier , Alexander D. Peleg , Carole Dulong , Eiichi Kowashi
IPC分类号： G06F752
CPC分类号： G06F17/10
摘要： The invention provides a method and apparatus for performing complex digital filters. According to one aspect of the invention, a method for performing a complex digital filter is described. The complex digital filter is performed using a set of data samples and a set of complex coefficients. In addition, the complex digital filter is performed using a inner and outer loop. The outer loop steps through a number of corresponding relationships between the set of complex coefficients and the set of data samples. The inner loop steps thorough each complex coefficient in the set of complex coefficients. Within the inner loop, the data sample corresponding to the current complex coefficient (the complex coefficient currently identified by the inner loop) is determined according to the current corresponding relationship (the corresponding relationship currently identified by the outer loop). Then, in response to receiving an instruction, eight data elements are read and used to generate a currently calculated complex number. These eight data elements were previously stored as packed data and include two representations of each of the components of the current complex coefficient and its current corresponding data sample. Each of these data elements is either the positive or negative of the component they represent. As a result of the manner in which these eight data elements are stored, the currently calculated complex number represents the product of the current complex coefficient and its current corresponding data sample. The currently calculated complex number is then added to the current output packed data.
摘要翻译：本发明提供一种用于执行复杂数字滤波器的方法和装置。根据本发明的一个方面，描述了一种用于执行复数数字滤波器的方法。使用一组数据样本和一组复系数来执行复数数字滤波器。另外，使用内循环和外循环执行复数数字滤波器。外循环遍历复系数集合和数据样本集之间的若干对应关系。内循环遍及复系数集合中的每个复系数。在内循环中，根据当前对应关系（当前由外循环确定的对应关系）确定对应于当前复系数（由内循环确定的复系数）的数据样本。然后，响应于接收到指令，读取并使用八个数据元素来生成当前计算的复数。这八个数据元素预先存储为打包数据，并且包括当前复系数及其当前相应数据样本的每个分量的两个表示。这些数据元素中的每一个都是它们表示的组件的正或负。作为存储这八个数据元素的方式的结果，当前计算的复数代表当前复系数和其当前相应数据样本的乘积。然后将当前计算的复数加到当前输出的打包数据中。

46. 发明授权

US06266686B1 Emptying packed data state during execution of packed data instructions 有权
标题翻译：在打包数据指令执行期间清空打包数据状态
公开(公告)号：US06266686B1
公开(公告)日：2001-07-24
申请号：US09262951
申请日：1999-03-04
申请人： David Bistry , Larry Mennemeier , Alexander D. Peleg , Carole Dulong , Eiichi Kowashi , Millind Mittal , Benny Eitan
发明人： David Bistry , Larry Mennemeier , Alexander D. Peleg , Carole Dulong , Eiichi Kowashi , Millind Mittal , Benny Eitan
IPC分类号： G06F9302
CPC分类号： G06F9/3013 , G06F9/30007 , G06F9/3001 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30109 , G06F9/30112 , G06F9/30134
摘要： A method in a computer system which includes receiving a first instruction which indicates indicates termination of execution of instructions which operate upon packed data stored in a first storage area. The first storage area is used for modifying data responsive to execution of floating point instructions. A plurality of tags is associated with the first storage area indicating that locations in the first storage area are either empty or non-empty responsive to the execution of the floating point instructions which modify data contained in the first storage area. Responsive to the receiving of the first instruction which indicates termination of execution of instructions which operate upon the packed data stored in the first storage area, the method sets only the plurality of tags to an empty state. In different embodiments, setting of the plurality of tags to a non-empty state occurs responsive to receiving a second instruction. The second instruction (or instructions) specifies an operation upon packed data stored in the first storage area. The setting of the plurality of tags indicates execution of instructions which operate upon the packed data. This method advantageously provides a means for clearing the packed data state at the end of blocks of packed data instructions to leave the floating point state in a clear condition for subsequent operations (e.g. floating point calculations).
摘要翻译：一种计算机系统中的方法，包括接收指示的第一指令，指示对存储在第一存储区域中的压缩数据进行操作的指令的执行的终止。第一个存储区域用于响应于浮点指令的执行来修改数据。响应于修改包含在第一存储区域中的数据的浮点指令的执行，多个标签与第一存储区域相关联，指示第一存储区域中的位置是空的或非空的。响应于接收指示终止对存储在第一存储区域中的打包数据进行操作的指令的第一指令，该方法仅将多个标签设置为空状态。在不同的实施例中，响应于接收第二指令而发生多个标签的设置为非空状态。第二指令（或指令）指定存储在第一存储区域中的压缩数据的操作。多个标签的设置指示对打包数据进行操作的指令的执行。该方法有利地提供了一种用于在打包数据指令的块结束时清除打包数据状态的装置，以使浮点状态处于用于后续操作（例如，浮点计算）的清楚状态。

47. 发明授权

US06170997B2 Method for executing instructions that operate on different data types stored in the same single logical register file 失效
标题翻译：用于执行对存储在同一单个逻辑寄存器文件中的不同数据类型进行操作的指令的方法
公开(公告)号：US06170997B2
公开(公告)日：2001-01-09
申请号：US08898720
申请日：1997-07-22
申请人： Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrik Lin , Romamohan R. Vakkalagadda
发明人： Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrik Lin , Romamohan R. Vakkalagadda
IPC分类号： G06F9302
CPC分类号： G06F9/3017 , G06F9/30036 , G06F9/30101 , G06F9/30105 , G06F9/30109 , G06F9/30112 , G06F9/30134 , G06F9/30189 , G06F9/384 , G06F9/45533 , G06F9/462
摘要： A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to one aspect of the invention, a data processing apparatus executes a first set of instructions of a first instruction type on what at least logically appears to software as a single logical register file. While the data processing apparatus is executing the first set of instructions, the single logical register file appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second instruction type using the logical register file. However, while the data processing apparatus is executing the first instruction, the logical register file appears to be operated as a stack referenced register file. Furthermore, the data processing apparatus alters all tags in a set of tags corresponding to the single logical register file to a non-empty state sometime between starting the execution of the first set of instructions and completing the execution of the first instruction. The tags identifying whether registers in the single logical register file are empty or non-empty.
摘要翻译：一种用于执行不同的指令集的方法，其使得处理器以对于各种操作系统技术是不可见的方式执行不同的数据类型操作，其促进良好的编程实践，并且对于现有的软件约定是不可见的。根据本发明的一个方面，数据处理设备执行第一指令类型的第一组指令，至少在软件上逻辑上显示为单个逻辑寄存器文件。当数据处理装置正在执行第一组指令时，单个逻辑寄存器文件似乎被操作为平坦寄存器文件。此外，数据处理装置使用逻辑寄存器文件执行第二指令类型的第一指令。然而，当数据处理装置正在执行第一指令时，逻辑寄存器文件似乎被操作为堆栈引用的寄存器文件。此外，在开始执行第一组指令并完成第一指令的执行之前的某个时刻，数据处理装置将对应于单个逻辑寄存器文件的一组标签中的所有标签改变为非空状态。识别单个逻辑寄存器文件中的寄存器是空还是非空的标签。

48. 发明授权

US6018351A Computer system performing a two-dimensional rotation of packed data representing multimedia information 失效
标题翻译：执行代表多媒体信息的打包数据的二维旋转的计算机系统
公开(公告)号：US6018351A
公开(公告)日：2000-01-25
申请号：US961549
申请日：1997-10-30
申请人： Larry M. Mennemeier , Alexander D. Peleg , Carole Dulong , Eiichi Kowashi , Millind Mittal , Benny Eitan
发明人： Larry M. Mennemeier , Alexander D. Peleg , Carole Dulong , Eiichi Kowashi , Millind Mittal , Benny Eitan
IPC分类号： G06F15/78 , G06T3/60 , G06F15/00
CPC分类号： G06T3/60 , G06F15/7864
摘要： A computer system for processing multimedia data, wherein the data is transformed from a first domain to a second domain by performing two dimensional rotation on the data. The computer system includes a memory having stored therein a set of packed data sequences having data elements representing the digital data, and a sequence of instructions for transforming the digital data from a first domain to a second domain. The instructions, when executed, cause the processor to generate a first set of intermediate results in response to the execution of a first instruction which multiples data elements of a first packed data sequence with corresponding elements of a third packed data sequence, wherein the data elements of the third packed data sequence represent either a sine or cosine function. The instructions then cause the processor to generate a second set of intermediate results in response to the execution of a second instruction which multiplies the data elements of a second packed data sequence with corresponding data elements of a fourth packed data sequence, wherein the data elements of the fourth packed data sequence representing either a sine or cosine function. A set of first set of final results is generated in response to the execution of a third instruction which performs an arithmetic operation between corresponding data elements of the first and second sets of intermediate results. The final results represent the digital data transformed into the second domain.
摘要翻译：一种用于处理多媒体数据的计算机系统，其中通过对数据执行二维旋转，将数据从第一域变换到第二域。计算机系统包括存储器，其中存储有具有表示数字数据的数据元素的一组打包数据序列，以及用于将数字数据从第一域变换到第二域的指令序列。所述指令在被执行时使得所述处理器响应于第一指令的执行而产生第一组中间结果，所述第一指令将第一打包数据序列的数据元素与第三打包数据序列的相应元素相乘，其中所述数据元素的第三打包数据序列表示正弦或余弦函数。然后指令使处理器响应于第二指令的执行而产生第二组中间结果，第二指令将第二打包数据序列的数据元素与第四打包数据序列的对应数据元素相乘，其中数据元素第四个压缩数据序列表示正弦或余弦函数。响应于执行第一和第二组中间结果的相应数据元素之间的算术运算的第三指令的执行而产生一组第一组最终结果。最终的结果代表了转换成第二个域的数字数据。

49. 发明授权

US5936872A Method and apparatus for storing complex numbers to allow for efficient complex multiplication operations and performing such complex multiplication operations 失效
标题翻译：用于存储复数以允许有效的复数乘法运算并执行这种复数乘法运算的方法和装置
公开(公告)号：US5936872A
公开(公告)日：1999-08-10
申请号：US575966
申请日：1995-12-20
申请人： Stephen A. Fischer , Larry M. Mennemeier , Alexander D. Peleg , Carole Dulong , Eiichi Kowashi
发明人： Stephen A. Fischer , Larry M. Mennemeier , Alexander D. Peleg , Carole Dulong , Eiichi Kowashi
IPC分类号： G06F7/48 , G06F7/52
CPC分类号： G06F7/4812
摘要： The invention provides a method and apparatus for storing complex data in formats which allow efficient complex multiplication operations to be performed and for performing such complex multiplication operations. According to one aspect of the invention, a method for multiplying complex numbers is provided for use in a data processing system. In response to receiving an instruction, eight data elements are read and used to generate a resulting complex number. These eight data elements were previously stored as packed data and include two representations of each of the components of a first and second complex number. Each of these representations is signed such that it represents either the positive or negative of said component. As a result of the manner in which these eight data elements are stored, the resulting complex number represents the product of the first and second complex numbers. According to another aspect of the invention, a machine-readable medium is described. This machine-readable medium has stored thereon data representing sequences of instructions which, when executed by a processor, cause that processor to perform the above described method.
摘要翻译：本发明提供一种用于以允许执行有效的复数乘法运算并执行这种复数乘法运算的格式存储复数数据的方法和装置。根据本发明的一个方面，提供一种用于复数的方法，用于数据处理系统。响应于接收到指令，读取并使用八个数据元素来产生所得到的复数。这八个数据元素预先存储为打包数据，并且包括第一和第二复数的每个组件的两个表示。这些表示中的每一个都被签名，使得它表示所述组件的正或负。作为存储这八个数据元素的方式的结果，所得到的复数代表第一和第二复数的乘积。根据本发明的另一方面，描述了一种机器可读介质。该机器可读介质上存储有表示指令序列的数据，该指令序列由处理器执行时使该处理器执行上述方法。

50. 发明授权

US5859997A Method for performing multiply-substrate operations on packed data 失效
标题翻译：对打包数据进行乘法减法运算的方法
公开(公告)号：US5859997A
公开(公告)日：1999-01-12
申请号：US699993
申请日：1996-08-20
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Wolf Witt , Carole Dulong , Eiichi Kowashi
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Wolf Witt , Carole Dulong , Eiichi Kowashi
IPC分类号： G06F7/544 , G06F9/00
CPC分类号： G06F9/30036 , G06F7/5443 , G06F2207/3828
摘要： A method and apparatus for including in a processor instructions for performing multiply-subtract operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least one of the data elements in this third packed data storing the result of performing a multiply-subtract operation on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法减法操作的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少一个数据元素存储对第一和第二打包数据中的数据元素进行乘法运算的结果。

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