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41. 发明申请

US20070158681A1 Power integrated circuit device having embedded high-side power switch 有权
标题翻译：电源集成电路器件具有嵌入式高端电源开关
公开(公告)号：US20070158681A1
公开(公告)日：2007-07-12
申请号：US11329268
申请日：2006-01-09
申请人： Sung-lyong Kim , Chang-ki Jeon , Jong-jib Kim , Jong-tae Hwang
发明人： Sung-lyong Kim , Chang-ki Jeon , Jong-jib Kim , Jong-tae Hwang
IPC分类号： H01L29/74
CPC分类号： H01L29/808 , H01L27/088
摘要： In one embodiment, a power integrated circuit device is provided. The power integrated circuit device includes a high-side power switch having a high voltage transistor and a low voltage transistor. The high voltage transistor has a gate, a source, and a drain, and is capable of withstanding a high voltage applied to its drain. The low voltage transistor has a gate, a source, and a drain, wherein the drain of the low voltage transistor is connected to the source of the high voltage transistor and the source of the low voltage transistor is connected to the gate of the high voltage transistor, and wherein a control signal is applied to the gate of the low voltage transistor from the power integrated circuit device. The high-side power switch is turned on when a predetermined voltage is applied to the source of the low voltage transistor, a voltage higher than the predetermined voltage is applied to the drain of the high voltage transistor, and a voltage level of the control signal becomes higher than the predetermined voltage by a threshold voltage of the low voltage transistor.
摘要翻译：在一个实施例中，提供了功率集成电路器件。功率集成电路装置包括具有高压晶体管和低压晶体管的高侧电源开关。高压晶体管具有栅极，源极和漏极，并且能够承受施加到其漏极的高电压。低压晶体管具有栅极，源极和漏极，其中低压晶体管的漏极连接到高压晶体管的源极，并且低压晶体管的源极连接到高电压的栅极晶体管，并且其中控制信号从功率集成电路器件施加到低电压晶体管的栅极。当向低电压晶体管的源极施加预定电压时，高侧电源开关接通，将高于预定电压的电压施加到高压晶体管的漏极，并且控制信号的电压电平通过低压晶体管的阈值电压变得高于预定电压。

42. 发明授权

US06600206B2 High voltage semiconductor device having high breakdown voltage isolation region 有权
标题翻译：具有高击穿电压隔离区域的高电压半导体器件
公开(公告)号：US06600206B2
公开(公告)日：2003-07-29
申请号：US10123007
申请日：2002-04-15
申请人： Chang-ki Jeon , Sung-Iyong Kim , Jong-jib Kim
发明人： Chang-ki Jeon , Sung-Iyong Kim , Jong-jib Kim
IPC分类号： H01L2900
CPC分类号： H01L29/7816 , H01L29/0615 , H01L29/063 , H01L29/0692 , H01L29/0696 , H01L29/1083 , H01L29/1095
摘要： A high voltage semiconductor device is provided. The high voltage semiconductor device includes a tow voltage region, a high voltage region, and a high breakdown voltage isolation region. The high voltage region is surrounded by the low voltage region and has corner portions at one side thereof. The high breakdown voltage isolation region has an isolation region for electrically separating the low and high voltage regions from each other and a lateral double diffused metal-oxide-semiconductor (DMOS) transistor for transmitting a signal from the low voltage region to the high voltage region. In particular, a drain region of the lateral DMOS transistor is disposed between the corner portions of the high voltage region, and opposite edges of the corner portions of the high voltage region and drain region of the lateral DMOS transistor are curved.
摘要翻译：提供高压半导体器件。高电压半导体器件包括丝束电压区域，高电压区域和高击穿电压隔离区域。高电压区域被低电压区域包围，并且在其一侧具有角部。高击穿电压隔离区域具有用于将低电压区域和高电压区域彼此电隔离的隔离区域和用于将信号从低电压区域传输到高电压区域的横向双扩散金属氧化物半导体（DMOS）晶体管。特别地，横向DMOS晶体管的漏极区域设置在高电压区域的角部之间，并且横向DMOS晶体管的高压区域和漏极区域的拐角部分的相对边缘是弯曲的。

43. 发明授权

US06489652B1 Trench DMOS device having a high breakdown resistance 失效
标题翻译：具有高耐击穿性的沟槽DMOS器件
公开(公告)号：US06489652B1
公开(公告)日：2002-12-03
申请号：US08742754
申请日：1996-11-01
申请人： Chang-Ki Jeon , Young-Soo Jang
发明人： Chang-Ki Jeon , Young-Soo Jang
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/42368
摘要： A trench DMOS device having improved breakdown characteristics. The trench DMOS device has a gate oxide layer which has a substantially flattened thick portion in the bottom of the trench and which is relatively thinner on the sidewalls. In greater detail, the trench DMOS device comprises a trench formed in a semiconductor substrate, said trench having sidewalls and a bottom, a gate polysilicon layer filled into said trench, and a gate oxide layer formed between said gate polysilicon layer and the sidewalls and bottom of said trench, wherein a bottom part of said gate oxide layer has a thickness greater than both sidewall parts thereof, and a central region of said bottom part is substantially flattened with a thickness greater than boundary regions thereof. Also disclosed is a novel method of fabricating a trench DMOS device.
摘要翻译：具有改进的击穿特性的沟槽DMOS器件。沟槽DMOS器件具有栅极氧化物层，其在沟槽的底部具有基本平坦的厚部分，并且在侧壁上相对较薄。更详细地，沟槽DMOS器件包括形成在半导体衬底中的沟槽，所述沟槽具有侧壁和底部，填充到所述沟槽中的栅极多晶硅层以及形成在所述栅极多晶硅层与侧壁和底部之间的栅极氧化物层的所述沟槽，其中所述栅极氧化物层的底部具有大于其两个侧壁部分的厚度，并且所述底部部分的中心区域大致平坦化，其厚度大于其边界区域。还公开了一种制造沟槽DMOS器件的新颖方法。

44. 发明授权

US06486512B2 Power semiconductor device having high breakdown voltage and method for fabricating the same 有权
标题翻译：具有高击穿电压的功率半导体器件及其制造方法
公开(公告)号：US06486512B2
公开(公告)日：2002-11-26
申请号：US09790815
申请日：2001-02-23
申请人： Chang-ki Jeon , Jong-jib Kim , Young-suk Choi , Chang-seong Choi , Min-whan Kim
发明人： Chang-ki Jeon , Jong-jib Kim , Young-suk Choi , Chang-seong Choi , Min-whan Kim
IPC分类号： H01L2976
CPC分类号： H01L29/0692 , H01L29/0696 , H01L29/7835
摘要： A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a source structure having a projected portion with a tip-shaped end portion on its center and formed so as to surround a predetermined region of right and left and upper portions of the projected portion. Two drain structures are formed in a predetermined region surrounded by the source structure. Extended drain structures are formed around the drain structures and the extended drain structures function as a channel with a field effect channel between sides of the projected portion of the source structure. Accordingly, since there are no drain structures on the tip of the projected portion of the source structure, although a radius of curvature of the tip of the projected portion is small, a decrease in a breakdown voltage of a device due to the small radius of curvature of the tip of the projected portion can be suppressed. As a result, a power semiconductor device having a small radius of curvature of the source structure and a high breakdown voltage can be provided.
摘要翻译：提供了功率半导体器件及其制造方法。功率半导体器件包括源结构，其具有在其中心具有尖端形状的端部的突出部分并且形成为围绕突出部分的左右上部的预定区域。在由源结构包围的预定区域中形成两个漏极结构。在漏极结构周围形成扩展的漏极结构，并且延伸的漏极结构用作具有源结构的突出部分的侧面之间的场效应沟道的沟道。因此，由于在源极结构的突出部分的尖端上没有漏极结构，尽管突出部分的尖端的曲率半径小，但是由于半径小的部件，器件的击穿电压降低可以抑制突出部分的尖端的弯曲。结果，可以提供具有较小的源结构曲率半径和高击穿电压的功率半导体器件。

45. 发明授权

US6087244A Methods of forming semiconductor-on-insulator devices including buried layers of opposite conductivity type 有权
标题翻译：形成绝缘体上半导体器件的方法，包括具有相反导电类型的掩埋层
公开(公告)号：US6087244A
公开(公告)日：2000-07-11
申请号：US300115
申请日：1999-04-27
申请人： Chang-Ki Jeon
发明人： Chang-Ki Jeon
IPC分类号： H01L21/762 , H01L21/02 , H01L21/20 , H01L21/304 , H01L21/76 , H01L21/763 , H01L21/84 , H01L27/12
CPC分类号： H01L21/76264 , H01L21/763 , H01L21/84 , H01L27/1203 , H01L21/76275 , H01L21/76286 , Y10S438/938
摘要： Semiconductor-on-insulator (SOI) devices are fabricated by forming first and second semiconductor layers of opposite conductivity types, at a first face of a substrate. An insulating layer is formed on the first and second semiconductor layers. A trench is formed through the insulating layer extending between the first and second semiconductor layers and extending into the substrate. A portion of the substrate is removed from a second face which is opposite the first face, to define respective first and second active regions on the respective first and second semiconductor layers.
摘要翻译：绝缘体上半导体（SOI）器件通过在衬底的第一面上形成具有相反导电类型的第一和第二半导体层来制造。绝缘层形成在第一和第二半导体层上。通过在第一和第二半导体层之间延伸并延伸到衬底中的绝缘层形成沟槽。从与第一面相对的第二面去除衬底的一部分，以在相应的第一和第二半导体层上限定相应的第一和第二有源区。

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