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41. 发明申请

US20110153997A1 Bit Range Isolation Instructions, Methods, and Apparatus 有权
标题翻译：位范围隔离说明，方法和设备
公开(公告)号：US20110153997A1
公开(公告)日：2011-06-23
申请号：US12645307
申请日：2009-12-22
申请人： Maxim Loktyukhin , Eric W. Mahurin , Bret L. Toll , Martin G. Dixon , Sean P. Mirkes , David L. Kreitzer , El Moustapha Ould-Ahmed-Vall , Vinodh Gopal
发明人： Maxim Loktyukhin , Eric W. Mahurin , Bret L. Toll , Martin G. Dixon , Sean P. Mirkes , David L. Kreitzer , El Moustapha Ould-Ahmed-Vall , Vinodh Gopal
IPC分类号： G06F9/305 , G06F9/30 , G06F12/02
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30029 , G06F9/30094 , G06F9/3802
摘要： Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.
摘要翻译：接收指示源操作数和目标操作数的指令。将结果存储在目标操作数中以响应指令。结果操作数可以具有：（1）具有第一端的第一范围，其中每个位在相应位置中的每个位与源操作数的位相同的指令明确地指定; 和（2）与相应位置中的源操作数的位的值无关的所有位都具有相同值的第二范围。不管移动第一范围的结果相对于源操作数的相应位置中相同值的位，执行指令都可以完成，而不考虑结果中第一个位的位置。还公开了执行这些指令的执行单元，具有执行这种指令的处理器的计算机系统以及存储这种指令的机器可读介质。

42. 发明申请

US20110153983A1 Gathering and Scattering Multiple Data Elements 有权
标题翻译：收集和散布多个数据元素
公开(公告)号：US20110153983A1
公开(公告)日：2011-06-23
申请号：US12644440
申请日：2009-12-22
申请人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
IPC分类号： G06F9/38 , G06F15/76 , G06F9/06 , G06F12/08
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3865
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
摘要翻译：根据第一方面，可以通过以下方式来实现有效的数据传送操作：通过处理器设备解码指定在第一存储位置和第二存储位置之间的多个数据元素的传送操作的单个指令; 发出用于由处理器中的执行单元执行的单个指令; 在单个指令的执行期间检测异常的发生; 并且响应于异常，在传递异常之前将异常陷阱或中断传递给异常处理程序。

43. 发明授权

US07917734B2 Determining length of instruction with multiple byte escape code based on information from other than opcode byte 有权
标题翻译：基于除操作码字节以外的信息确定多字节转义码指令的长度
公开(公告)号：US07917734B2
公开(公告)日：2011-03-29
申请号：US10611164
申请日：2003-06-30
申请人： James S. Coke , Peter J. Ruscito , Masood Tahir , David B. Jackson , Ves A. Naydenov , Scott D. Rodgers , Bret L. Toll , Frank Binns
发明人： James S. Coke , Peter J. Ruscito , Masood Tahir , David B. Jackson , Ves A. Naydenov , Scott D. Rodgers , Bret L. Toll , Frank Binns
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30185
摘要： A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
摘要翻译：公开了用于对可变长度指令集中的指令进行解码的方法，装置和系统。该指令是一组新的指令之一，它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。定义新指令，可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度，其中每个输入与确定新指令中的每个指令的长度相关操作码地图。对于至少一个实施例，在不评估指令特定操作码的情况下确定新指令之一的长度。

44. 发明授权

US10203954B2 Instruction and logic to provide conversions between a mask register and a general purpose register or memory 有权
公开(公告)号：US10203954B2
公开(公告)日：2019-02-12
申请号：US13977732
申请日：2011-11-25
申请人： Elmoustapha Ould-Ahmed-Vall , Jesus Corbal , Robert Valentine , Bret L. Toll , Mark J. Charney
发明人： Elmoustapha Ould-Ahmed-Vall , Jesus Corbal , Robert Valentine , Bret L. Toll , Mark J. Charney
IPC分类号： G06F15/00 , G06F9/30 , G06F9/38
摘要： Instructions and logic provide conversions between a mask register and a general purpose register or memory. Some embodiments, responsive to an instruction specifying: a destination operand, a mask length corresponding to a number of mask data fields, and a source operand; values are read from data fields in the source operand, corresponding to the specified mask length, and stored to corresponding data fields in the destination operand specified by the instruction, wherein one of the source or the destination operands is a mask register. Values indicative of masked vector elements may be stored to any data fields in the destination operand other than the number of data fields corresponding to the specified mask length. For some embodiments, the other one of the source or the destination operands may be a general purpose register or a memory location.

45. 发明授权

US10037205B2 Instruction and logic to provide vector blend and permute functionality 有权
公开(公告)号：US10037205B2
公开(公告)日：2018-07-31
申请号：US13977734
申请日：2011-12-23
申请人： Robert Valentine , Bret L. Toll , Jesus Corbal , Jeffrey G. Wiedemeier , Sridhar Samudrala
发明人： Robert Valentine , Bret L. Toll , Jesus Corbal , Jeffrey G. Wiedemeier , Sridhar Samudrala
IPC分类号： G06F15/00 , G06F15/76 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30018 , G06F9/30032 , G06F9/3887
摘要： Vector blend and permute functionality are provided, responsive to instructions specifying: a destination vector register comprising fields to store vector elements, a first vector register, a vector element size, a second vector register, and a third operand. Indices are read from fields in the second register. Each index has a first selector portion and a second selector portion. Corresponding unmasked vector elements are stored to fields of the destination register, wherein each vector element, responsive to the respective first selector portion having a first value, is copied to an intermediate vector from a corresponding data field of the first register, and responsive to the respective first selector portion having a second value, is copied to the intermediate vector from a corresponding data field of the third operand. Then unmasked data fields of the destination are replaced by data fields in the intermediate vector indexed by the corresponding second selector portions.

46. 发明授权

US09575757B2 Efficient zero-based decompression 有权
标题翻译：高效的零基减压
公开(公告)号：US09575757B2
公开(公告)日：2017-02-21
申请号：US13991858
申请日：2011-12-30
申请人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles R. Yount , Bret L. Toll
发明人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles R. Yount , Bret L. Toll
IPC分类号： G06F9/30 , H03M7/46
CPC分类号： G06F9/30018 , G06F9/30036 , H03M7/46
摘要： A processor core including a hardware decode unit to decode vector instructions for decompressing a run length encoded (RLE) set of source data elements and an execution unit to execute the decoded instructions. The execution unit generates a first mask by comparing set of source data elements with a set of zeros and then counts the trailing zeros in the mask. A second mask is made based on the count of trailing zeros. The execution unit then copies the set of source data elements to a buffer using the second mask and then reads the number of RLE zeros from the set of source data elements. The buffer is shifted and copied to a result and the set of source data elements is shifted to the right. If more valid data elements are in the set of source data elements this is repeated until all valid data is processed.
摘要翻译：一种处理器核心，包括硬件解码单元，用于解码用于解压缩源数据元素的游程长度编码（RLE）集合的向量指令和执行单元以执行解码的指令。执行单元通过将源数据元素的集合与一组零进行比较来生成第一掩码，然后计数掩码中的尾随零。第二个掩码基于尾随零的计数。执行单元然后使用第二掩码将源数据元素集合复制到缓冲器，然后从源数据元素集合读取RLE零的数目。将缓冲区移位并复制到结果，并将源数据元素集合向右移动。如果源数据元素集合中有更多有效的数据元素，则重复此操作，直到处理所有有效数据。

47. 发明申请

US20160364308A1 PROVIDING AUTONOMOUS SELF-TESTING OF A PROCESSOR 有权
标题翻译：提供处理器的自动自检
公开(公告)号：US20160364308A1
公开(公告)日：2016-12-15
申请号：US14737768
申请日：2015-06-12
申请人： Vedvyas Shanbhogue , Eric Rasmussen , Deep K. Buch , Gordon McFadden , Kameswar Subramaniam , Amy L. Santoni , Willard M. Wiseman , Bret L. Toll
发明人： Vedvyas Shanbhogue , Eric Rasmussen , Deep K. Buch , Gordon McFadden , Kameswar Subramaniam , Amy L. Santoni , Willard M. Wiseman , Bret L. Toll
IPC分类号： G06F11/263 , G06F11/22
CPC分类号： G06F11/2635 , G06F11/1417 , G06F11/1433 , G06F11/2242 , G06F11/2268 , G06F11/27
摘要： In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch identifier associated with a test patch and a second field to store a test mode indicator to request a core functionality test, and a microcode storage to store microcode to be executed by the at least one core. Responsive to the test patch identifier, the microcode may access a firmware interface table and obtain the test patch from a non-volatile storage according to an address obtained from the firmware interface table. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括至少一个核心，功率管理单元，其具有第一测试寄存器，该第一测试寄存器包括第一字段以存储与测试补丁相关联的测试补丁标识符，以及第二字段以存储测试模式指示符以请求核心功能测试，以及微代码存储器，用于存储由所述至少一个核执行的微代码。响应于测试补丁标识符，微代码可以根据从固件接口表获得的地址从非易失性存储器访问固件接口表并获得测试补丁。描述和要求保护其他实施例。

48. 发明授权

US09513871B2 Floating point round-off amount determination processors, methods, systems, and instructions 有权
标题翻译：浮点数四舍五入确定处理器，方法，系统和说明
公开(公告)号：US09513871B2
公开(公告)日：2016-12-06
申请号：US13977257
申请日：2011-12-30
申请人： Cristina S. Anderson , Bret L. Toll , Robert Valentine , Simon Rubanovich , Amit Gradstein
发明人： Cristina S. Anderson , Bret L. Toll , Robert Valentine , Simon Rubanovich , Amit Gradstein
IPC分类号： G06F7/483 , G06F9/30 , G06F7/499
CPC分类号： G06F9/3001 , G06F7/483 , G06F7/49947 , G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/3013
摘要： A method of an aspect includes receiving a floating point round-off amount determination instruction. The instruction indicates a source of one or more floating point data elements, indicates a number of fraction bits after a radix point, and indicates a destination storage location. A result including one or more result floating point data elements is stored in the destination storage location in response to the floating point round-off amount determination instruction. Each of the one or more result floating point data elements includes a difference between a corresponding floating point data element of the source in a corresponding position, and a rounded version of the corresponding floating point data element of the source that has been rounded to the indicated number of the fraction bits. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译：一种方面的方法包括接收浮点舍入量确定指令。该指令指示一个或多个浮点数据元素的源，指示小数点之后的小数位数，并指示目的地存储位置。包括一个或多个结果浮点数据元素的结果响应于浮点舍入量确定指令被存储在目的地存储位置中。一个或多个结果浮点数据元素中的每一个包括相应位置的源的相应浮点数据元素与已被舍入到指示的源的相应浮点数据元素的舍入版本之间的差小数位数。公开了其它方法，装置，系统和指令。

49. 发明授权

US09489196B2 Multi-element instruction with different read and write masks 有权
标题翻译：具有不同读写掩码的多元素指令
公开(公告)号：US09489196B2
公开(公告)日：2016-11-08
申请号：US13997998
申请日：2011-12-23
申请人： Mikhail Plotnikov , Andrey Naraikan , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Bret L. Toll , Jesus Corbal
发明人： Mikhail Plotnikov , Andrey Naraikan , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Bret L. Toll , Jesus Corbal
IPC分类号： G06F7/76 , G06F9/30
CPC分类号： G06F9/3013 , G06F7/764 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30036
摘要： A method is described that includes reading a first read mask from a first register. The method also includes reading a first vector operand from a second register or memory location. The method also includes applying the read mask against the first vector operand to produce a set of elements for operation. The method also includes performing an operation of the set elements. The method also includes creating an output vector by producing multiple instances of the operation's result. The method also includes reading a first write mask from a third register, the first write mask being different than the first read mask. The method also includes applying the write mask against the output vector to create a resultant vector. The method also includes writing the resultant vector to a destination register.
摘要翻译：描述了一种包括从第一寄存器读取第一读取掩码的方法。该方法还包括从第二寄存器或存储器位置读取第一向量操作数。该方法还包括对第一向量操作数应用读取掩码以产生用于操作的一组元素。该方法还包括执行设定元件的操作。该方法还包括通过产生操作结果的多个实例来创建输出向量。该方法还包括从第三寄存器读取第一写掩码，第一写掩码不同于第一读掩码。该方法还包括针对输出向量应用写掩码以产生合成矢量。该方法还包括将结果矢量写入目的地寄存器。

50. 发明授权

US09354877B2 Systems, apparatuses, and methods for performing mask bit compression 有权
标题翻译：用于执行掩码位压缩的系统，设备和方法
公开(公告)号：US09354877B2
公开(公告)日：2016-05-31
申请号：US13992709
申请日：2011-12-23
申请人： Bret L. Toll , Robert Valentine , Jesus Corbal , Elmoustapha Ould-Ahmed-Vall , Mark J. Charney
发明人： Bret L. Toll , Robert Valentine , Jesus Corbal , Elmoustapha Ould-Ahmed-Vall , Mark J. Charney
IPC分类号： G06F9/22 , G06F9/30
CPC分类号： G06F9/30018 , G06F9/30025 , G06F9/30098 , G06F9/30181
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor mask bit compression in response to a single mask bit compression instruction that includes a source writemask register operand, a destination writemask register operand, and an opcode are described.
摘要翻译：描述了在计算机处理器中执行屏蔽位压缩的系统，装置和方法的实施例，其响应于包括源写入寄存器操作数，目的地写入寄存器操作数和操作码的单个掩码位压缩指令。

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