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41. 发明授权

US08447955B2 Efficient memory update process for well behaved applications executing on a weakly-ordered processor 失效
标题翻译：在弱有序处理器上执行的良好行为应用程序的高效内存更新过程
公开(公告)号：US08447955B2
公开(公告)日：2013-05-21
申请号：US12259699
申请日：2008-10-28
申请人： Andrew Dunshea , Satya Prakash Sharma , Mysore Sathyanarayana Srinivas
发明人： Andrew Dunshea , Satya Prakash Sharma , Mysore Sathyanarayana Srinivas
IPC分类号： G06F9/30
CPC分类号： G06F12/0837 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3857
摘要： A multiprocessor data processing system (MDPS) with a weakly-ordered architecture providing processing logic for substantially eliminating issuing sync instructions after every store instruction of a well-behaved application. Instructions of a well-behaved application are translated and executed by a weakly-ordered processor. The processing logic includes a lock address tracking utility (LATU), which provides an algorithm and a table of lock addresses, within which each lock address is stored when the lock is acquired by the weakly-ordered processor. When a store instruction is encountered in the instruction stream, the LATU compares the target address of the store instruction against the table of lock addresses. If the target address matches one of the lock addresses, indicating that the store instruction is the corresponding unlock instruction (or lock release instruction), a sync instruction is issued ahead of the store operation. The sync causes all values updated by the intermediate store operations to be flushed out to the point of coherency and be visible to all processors.
摘要翻译：具有弱有序体系结构的多处理器数据处理系统（MDPS）提供处理逻辑，用于在运行良好的应用的每个存储指令之后基本上消除发出同步指令。良好的应用程序的指令由弱有序的处理器转换和执行。处理逻辑包括一个锁定地址跟踪实用程序（LATU），它提供一种算法和一个锁定地址表，当弱锁定处理器获取锁时，锁存地址被存储在该地址中。当在指令流中遇到存储指令时，LATU将存储指令的目标地址与锁定地址表进行比较。如果目标地址与其中一个锁定地址匹配，指示存储指令是相应的解锁指令（或锁定释放指令），则在存储操作之前发出同步指令。同步使得由中间存储操作更新的所有值被刷新到一致性点，并且对于所有处理器可见。

42. 发明授权

US08037203B2 User defined preferred DNS reference 失效
标题翻译：用户定义的首选DNS参考
公开(公告)号：US08037203B2
公开(公告)日：2011-10-11
申请号：US10782668
申请日：2004-02-19
申请人： Jos Manuel Accapadi , Mathew Accapadi , William Lee Britton , Andrew Dunshea , Dirk Michel
发明人： Jos Manuel Accapadi , Mathew Accapadi , William Lee Britton , Andrew Dunshea , Dirk Michel
IPC分类号： G06F15/173
CPC分类号： H04L61/1511
摘要： Methods, systems, and products are disclosed for user defined preferred DNS routing that include mapping for a user in a data communications application a domain name of a network host to a network address for a preferred DNS server, wherein the preferred DNS server has a network address for the domain name; receiving from the user a request for access to a resource accessible through the network host; and routing to the preferred DNS server a DNS request for the network address of the network host, the DNS request including the domain name of the network host. In typical embodiments, mapping a domain name to a network address for a preferred DNS server is carried out by storing, through the data communication application, the domain name in association with the network address for a preferred DNS server in a data structure in computer memory.
摘要翻译：公开了用于用户定义的优选DNS路由的方法，系统和产品，其包括将数据通信应用中的用户映射到网络主机的域名到优选DNS服务器的网络地址，其中优选DNS服务器具有网络地址为域名; 从用户接收对通过网络主机可访问的资源的访问请求; 并将首选DNS服务器路由到网络主机的网络地址的DNS请求，DNS请求包括网络主机的域名。在典型的实施例中，将域名映射到优选DNS服务器的网络地址是通过数据通信应用与计算机存储器中的数据结构中的优选DNS服务器的网络地址相关联地存储域名来执行的。

43. 发明授权

US07721047B2 System, method and computer program product for application-level cache-mapping awareness and reallocation requests 有权
标题翻译：系统，方法和计算机程序产品，用于应用级缓存映射感知和重新分配请求
公开(公告)号：US07721047B2
公开(公告)日：2010-05-18
申请号：US11006112
申请日：2004-12-07
申请人： Andrew Dunshea , Diane Garza Flemming
发明人： Andrew Dunshea , Diane Garza Flemming
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/0864 , G06F12/1045
摘要： In view of the foregoing, the shortcomings of the prior art cache optimization techniques, the present invention provides an improved method, system, and computer program product that can optimize cache utilization. In one embodiment, an application requests a kernel cache map from a kernel service and the application receives the kernel. The application designs an optimum cache footprint for a data set from said application. The objects, advantages and features of the present invention will become apparent from the following detailed description. In one embodiment of the present invention, the application transmits a memory reallocation order to a memory manager. In one embodiment of the present invention, the step of the application transmitting a memory reallocation order to the memory manager further comprises the application transmitting a memory reallocation order containing the optimum cache footprint to the memory manager. In one embodiment of the present invention, the step of the application transmitting a memory reallocation order to a memory manager further comprises the application transmitting the memory reallocation order containing to a reallocation services tool within the memory manager.
摘要翻译：鉴于上述情况，现有技术的高速缓存优化技术的缺点在于本发明提供了可以优化高速缓存利用的改进的方法，系统和计算机程序产品。在一个实施例中，应用程序从内核服务请求内核缓存映射，并且应用程序接收内核。该应用程序为来自所述应用的数据集设计了最佳缓存占用。从下面的详细描述中，本发明的目的，优点和特征将变得显而易见。在本发明的一个实施例中，应用程序将存储器重新分配顺序发送到存储器管理器。在本发明的一个实施例中，向存储器管理器发送存储器重分配顺序的应用程序的步骤还包括向存储器管理器发送包含最佳高速缓存占用空间的存储器重新分配顺序的应用程序。在本发明的一个实施例中，向存储器管理器发送存储器重新分配顺序的应用程序的步骤还包括将包含在存储器管理器内的重新分配服务工具的存储器重新分配顺序传送的应用。

44. 发明申请

US20090254730A1 Memory Pacing 失效
标题翻译：内存起搏
公开(公告)号：US20090254730A1
公开(公告)日：2009-10-08
申请号：US12478830
申请日：2009-06-05
申请人： Andrew Dunshea , Jos Manuel Accapadi , Catherine Moriarty Nunez
发明人： Andrew Dunshea , Jos Manuel Accapadi , Catherine Moriarty Nunez
IPC分类号： G06F12/02
CPC分类号： G06F12/1009 , Y10S707/99953 , Y10S707/99957
摘要： A method, system, and program for managing memory page requests in a multi-processor data processing system determines a threshold value of available memory, and dynamically adjusts an allocation time to fulfill a page request if the available memory is below a threshold value. The allocation time to fulfill the page request is based upon a percentage of available memory pages once a page stealer commences a scan for pages. An allocation wait time is inversely proportionally adjusted depending upon the percentage of available memory. The allocation wait time has a duration that increases in time as the percentage of available memory decreases and decreases in time as the percentage of available memory increases. More specifically, an average time per page to allocate a page including a scan time for the scan in computing the average time is determined. Then a tunable value is applied to the average time to determine a wait time. In a preferred embodiment, user defined values are received that would control the allocation wait time before fulfilling a page request.
摘要翻译：用于管理多处理器数据处理系统中的存储器页面请求的方法，系统和程序确定可用存储器的阈值，并且如果可用存储器低于阈值，则动态地调整分配时间以满足页面请求。一旦页面窃取器开始扫描页面，则完成页面请求的分配时间基于可用内存页面的百分比。分配等待时间根据可用内存的百分比进行反比例调整。分配等待时间具有随时间增加的持续时间，随着可用内存的百分比的增加，可用内存的百分比随时间而减少。更具体地，确定在计算平均时间时分配包括用于扫描的扫描时间的页面的每页的平均时间。然后将可调值应用于平均时间以确定等待时间。在优选实施例中，接收用户定义的值，其将在满足页面请求之前控制分配等待时间。

45. 发明授权

US07543124B1 Method for preventing page replacement of unreferenced read-ahead file pages 失效
标题翻译：防止未引用的预读文件页面更换页面的方法
公开(公告)号：US07543124B1
公开(公告)日：2009-06-02
申请号：US12170218
申请日：2008-07-09
申请人： Mathew Accapadi , Dirk Michel , Andrew Dunshea , Jos M. Accapadi
发明人： Mathew Accapadi , Dirk Michel , Andrew Dunshea , Jos M. Accapadi
IPC分类号： G06F12/07 , G06F12/57
CPC分类号： G06F12/126
摘要： A computer-implemented system, method, and program product is disclosed for managing memory pages in a memory that includes a page replacement function. The method includes detecting that a sequence of pages is read by an application into the memory. The method continues by initiating a read-ahead to access a plurality of pages including the sequence of pages and a next page that has not yet been read, and storing the plurality in a page frame table of the memory. During the read-ahead, the method sets a soft-pin bit in the page frame table corresponding to each of the pages of the plurality of pages in the read-ahead. Each the soft-pin bit temporarily reserves its respective page from replacement by the page replacement function.
摘要翻译：公开了一种用于管理包括页面替换功能的存储器中的存储器页面的计算机实现的系统，方法和程序产品。该方法包括检测一系列页面被应用程序读入存储器。该方法继续通过启动预读来访问包括页序列的多个页面和尚未被读取的下一页面，并将多个页面存储在存储器的页面框架表中。在预读期间，该方法设置与预读中的多个页面中的每页相对应的页框表中的软针位。每个软针位通过页面更换功能临时保留其替换页面。

46. 发明申请

US20090113239A1 METHOD AND APPARATUS FOR INSTRUCTION TRACE REGISTERS 有权
标题翻译：指令跟踪寄存器的方法和装置
公开(公告)号：US20090113239A1
公开(公告)日：2009-04-30
申请号：US11924192
申请日：2007-10-25
申请人： Jos Manuel Accapadi , Andrew Dunshea , Miho Ogishima , Suzanne Shi
发明人： Jos Manuel Accapadi , Andrew Dunshea , Miho Ogishima , Suzanne Shi
IPC分类号： G06F9/30 , G06F11/07 , G06F9/312
CPC分类号： G06F9/30101
摘要： A computer implemented method, apparatus, and computer usable program product for utilizing instruction trace registers. In one embodiment, a value in a target processor register in a plurality of processor registers is updated in response to executing an instruction associated with program code. In response to updating the value in the target processor register, an address for the instruction is copied from an instruction address register into an instruction trace register associated with the target processor register. The instruction trace register holds the address of the instruction that updated the value stored in the target processor register.
摘要翻译：一种用于使用指令跟踪寄存器的计算机实现的方法，装置和计算机可用程序产品。在一个实施例中，响应于执行与程序代码相关联的指令，更新多个处理器寄存器中的目标处理器寄存器中的值。响应更新目标处理器寄存器中的值，将指令的地址从指令地址寄存器复制到与目标处理器寄存器相关联的指令跟踪寄存器中。指令跟踪寄存器保存更新存储在目标处理器寄存器中的值的指令的地址。

47. 发明申请

US20080256324A1 IMPLEMENTING A FAST FILE SYNCHRONIZATION IN A DATA PROCESSING SYSTEM 失效
标题翻译：在数据处理系统中实现快速文件同步
公开(公告)号：US20080256324A1
公开(公告)日：2008-10-16
申请号：US12143552
申请日：2008-06-20
申请人： JOS M. ACCAPADI , Mathew Accapadi , Andrew Dunshea , Dirk Michel
发明人： JOS M. ACCAPADI , Mathew Accapadi , Andrew Dunshea , Dirk Michel
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F3/0601 , G06F12/0866 , G06F2003/0692 , G06F2212/311
摘要： A system and method for implementing a fast file synchronization in a data processing system. A memory management unit divides a file stored in system memory into a collection of data block groups. In response to a master (e.g., processing unit, peripheral, etc.) modifying a first data block group among the collection of data block groups, the memory management unit writes a first block group number associated with the first data block group to system memory. In response to a master modifying a second data block group, the memory management unit writes the first data block group to a hard disk drive and writes a second data block group number associated with the second data block group to system memory. In response to a request to update modified data block groups of the file stored in the system memory to the hard disk drive, the memory management unit writes the second data block to the hard disk drive.
摘要翻译：一种用于在数据处理系统中实现快速文件同步的系统和方法。存储器管理单元将存储在系统存储器中的文件划分成数据块组的集合。响应于在数据块组的集合中修改第一数据块组的主（例如，处理单元，外围设备等），存储器管理单元将与第一数据块组相关联的第一块组号写入系统存储器。响应于主修改第二数据块组，存储器管理单元将第一数据块组写入硬盘驱动器，并将与第二数据块组相关联的第二数据块组编号写入系统存储器。响应于将存储在系统存储器中的文件的修改的数据块组更新到硬盘驱动器的请求，存储器管理单元将第二数据块写入硬盘驱动器。

48. 发明申请

US20080168457A1 METHOD FOR TRADING RESOURCES BETWEEN PARTITIONS OF A DATA PROCESSING SYSTEM 失效
标题翻译：用于在数据处理系统的分组之间交换资源的方法
公开(公告)号：US20080168457A1
公开(公告)日：2008-07-10
申请号：US11621637
申请日：2007-01-10
申请人： JOS MANUEL ACCAPADI , ANDREW DUNSHEA , DIANE GARZA FLEMMING , CATHERINE MORIARTY NUNEZ
发明人： JOS MANUEL ACCAPADI , ANDREW DUNSHEA , DIANE GARZA FLEMMING , CATHERINE MORIARTY NUNEZ
IPC分类号： G06F9/46
CPC分类号： G06F9/5077
摘要： A method is provided for a data processing system configured to include multiple logical partitions, wherein resources of the system are selectively allocated among respective partitions. In the method, an entity such as a Partition Load Manager or a separate background process is used to manage resources based on locality levels. The method includes the step of evaluating the allocation of resources to each of the partitions at a particular time, in order to select a partition having at least one resource considered to be of low desirability due to its level of locality with respect to the selected partition. The method further comprises identifying each of the other partitions that has a resource matching the resource of low desirability, and determining the overall benefit to the system that would result from trading the resource of low desirability for the matching resource of each of the identified partitions. Resources are reallocated to trade the resource of low desirability for the matching resource of the identified partition that is determined to provide the greatest overall benefit for the system, provided that at least some overall system benefit will result from the reallocation.
摘要翻译：提供了一种用于数据处理系统的方法，所述数据处理系统被配置为包括多个逻辑分区，其中所述系统的资源在各个分区之间被选择性地分配。在该方法中，使用诸如分区加载管理器或单独的后台进程的实体来基于地点级别来管理资源。该方法包括在特定时间评估对每个分区的资源分配的步骤，以便由于其相对于所选择的分区的局部性水平而选择具有被认为是低可取性的至少一个资源的分区。该方法还包括识别具有与低可靠性的资源匹配的资源的每个其他分区，以及确定由对于每个所识别的分区的匹配资源的低期望性的资源进行交易而导致的系统的总体利益。重新分配资源以交换被确定为系统提供最大整体利益的所识别分区的匹配资源的低可用性资源，前提是至少部分整体系统利益将由重新分配产生。

49. 发明申请

US20080148274A1 Scheduling Compatible Threads in a Simultaneous Multi-Threading Processor Using Cycle Per Instruction Value Occurred During Identified Time Interval 有权
标题翻译：在同一个多线程处理器中调度兼容的线程使用周期每个指令值在确定的时间间隔期间发生
公开(公告)号：US20080148274A1
公开(公告)日：2008-06-19
申请号：US12036804
申请日：2008-02-25
申请人： Jos Manuel Accapadi , Andrew Dunshea , Dirk Michel , Mysore Sathyanarayana Srivivas
发明人： Jos Manuel Accapadi , Andrew Dunshea , Dirk Michel , Mysore Sathyanarayana Srivivas
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F2209/483
摘要： Identifying compatible threads in a Simultaneous Multithreading (SMT) processor environment is provided by calculating a performance metric, such as cycles per instruction (CPI), that occurs when two threads are running on the SMT processor. The CPI that is achieved when both threads were executing on the SMT processor is determined. If the CPI that was achieved is better than the compatibility threshold, then information indicating the compatibility is recorded. When a thread is about to complete, the scheduler looks at the run queue from which the completing thread belongs to dispatch another thread. The scheduler identifies a thread that is (1) compatible with the thread that is still running on the SMT processor (i.e., the thread that is not about to complete), and (2) ready to execute. The CPI data is continually updated so that threads that are compatible with one another are continually identified.
摘要翻译：通过计算在SMT处理器上运行两个线程时发生的性能指标（例如每个指令周期（CPI））来提供在同时多线程（SMT）处理器环境中识别兼容线程。确定在两个线程在SMT处理器上执行时实现的CPI。如果实现的CPI优于兼容性阈值，则记录指示兼容性的信息。当线程即将完成时，调度程序将查看完成线程所属的运行队列，以调度另一个线程。调度程序标识（1）与SMT处理器上仍然运行的线程（即，即将完成的线程）兼容的线程，以及（2）准备执行。持续更新CPI数据，以便不断地识别彼此兼容的线程。

50. 发明申请

US20070288941A1 SHARING KERNEL SERVICES AMONG KERNELS 有权
标题翻译：在KERNELS共享KERNEL服务
公开(公告)号：US20070288941A1
公开(公告)日：2007-12-13
申请号：US11422656
申请日：2006-06-07
申请人： Andrew Dunshea , Diane G. Flemming
发明人： Andrew Dunshea , Diane G. Flemming
IPC分类号： G06F9/46
CPC分类号： G06F9/5077
摘要： Sharing kernel services among kernels, including receiving, by a partition manager from an application in a logical partition, a first system call for a kernel service from a first kernel, the first system call having form and content compatible with the first kernel, generating, in dependence upon the first system call, a second system call for the kernel service from a second kernel, the second system call having form and content compatible with the second kernel, and sending the second system call through the partition manager to the second kernel for execution.
摘要翻译：在内核之间共享内核服务，包括由分区管理器从逻辑分区中的应用程序接收来自第一内核的内核服务的第一系统调用，第一系统调用具有与第一内核兼容的形式和内容，根据第一系统调用，第二系统调用来自第二内核的内核服务，第二系统调用具有与第二内核兼容的形式和内容，并且通过分区管理器将第二系统调用发送到第二内核，用于执行。

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