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41. 发明授权

US06937523B2 Neighbor effect cancellation in memory array architecture 失效
标题翻译：内存阵列架构中的邻居效应消除
公开(公告)号：US06937523B2
公开(公告)日：2005-08-30
申请号：US10696728
申请日：2003-10-27
申请人： Noam Eshel
发明人： Noam Eshel
IPC分类号： G11C16/28 , G11C16/06
CPC分类号： G11C16/28
摘要： Non-volatile memory (NVM) cells are sensed using a forced neighbor signal to eliminate improper readings generated by a neighbor effect. A selected NVM cell is sensed using a near-ground signal by applying a potential to a first terminal, coupling a second terminal to ground, and then decoupling the second terminal and comparing the resulting cell signal with a reference signal as both signals are developing (i.e., increasing from ground). A forced neighbor signal is applied to one more neighboring cells such that as the sensed cell signal develops (increases from ground), the forced neighbor signal develops at a similar rate, thereby maintaining a voltage across the neighboring cells close to zero and thus preventing leakage of the sensed cell signal through the neighbor cell(s). A dc sensing approach utilizes a current source and grounded resistor to minimize leakage through the neighbor cell(s).
摘要翻译：使用强制相邻信号感测非易失性存储器（NVM）单元，以消除由相邻效应产生的不正确读取。使用近地信号，通过向第一终端施加电位，将第二终端耦合到地，然后将第二终端解耦并在两个信号正在发展时将所得到的信号信号与参考信号进行比较，来使用近地信号来感测选定的NVM单元即从地面增加）。强制相邻信号被施加到一个更邻近的小区，使得随着感测到的小区信号的发展（从地面增加），强制邻居信号以相似的速率发展，从而保持邻近小区的电压接近零，从而防止泄漏的感测单元信号通过相邻单元。直流感测方法利用电流源和接地电阻来最小化通过相邻电池的泄漏。

42. 发明申请

US20030074611A1 Efficient test structure for non-volatile memory and other semiconductor integrated circuits 有权
标题翻译：非易失性存储器和其他半导体集成电路的高效测试结构
公开(公告)号：US20030074611A1
公开(公告)日：2003-04-17
申请号：US09975064
申请日：2001-10-10
申请人： Tower Semiconductor Ltd.
发明人： Ishai Nachumovsky
IPC分类号： G11C029/00
CPC分类号： G11C29/006 , G11C29/48
摘要： A test system includes a test wafer having non-volatile memory dies and an exposed set of pads. A probe wafer includes test circuitry, a first set of pads exposed at a first surface, a second set of pads exposed at a second surface (opposite the first surface), and an interconnect structure. The interconnect structure includes traces that extend through the probe card or around the edges of the probe card, between the first and second surfaces. A prober aligns the test wafer with the probe wafer, such that the pads of the test wafer contact the first set of pads of the probe wafer. The prober further contacts the second set of pads of the probe wafer, and provides connections between these pads and a tester. The probe wafer is fabricated using semiconductor processing techniques, so that precise alignment exists between the test wafer and the probe wafer.
摘要翻译：测试系统包括具有非易失性存储器管芯和暴露的焊盘的测试晶片。探针晶片包括测试电路，在第一表面暴露的第一组焊盘，在第二表面（与第一表面相对）暴露的第二组焊盘，以及互连结构。互连结构包括在第一和第二表面之间延伸穿过探针卡或探针卡的边缘周围的迹线。探测器将测试晶片与探针晶片对准，使得测试晶片的焊盘接触探针晶片的第一组焊盘。探测器进一步接触探针晶片的第二组焊盘，并提供这些焊盘和测试仪之间的连接。使用半导体处理技术制造探针晶片，使得在测试晶片和探针晶片之间精确对准。

43. 发明申请

US20030071288A1 Two-bit split-gate non-volatile memory transistor 审中-公开
标题翻译：两位分闸非易失性存储晶体管
公开(公告)号：US20030071288A1
公开(公告)日：2003-04-17
申请号：US09975049
申请日：2001-10-10
申请人： Tower Semiconductor Ltd.
发明人： Ishai Nachumovsky
IPC分类号： H01L027/148
CPC分类号： H01L27/11521 , G11C16/0475 , H01L27/115 , H01L29/7887
摘要： A 2-bit non-volatile memory (NVM) transistor having a pair of isolated floating gate electrodes is provided. One of the floating gate electrodes is located over a first source/drain region, and a first adjacent end of a channel region. The other floating gate electrode is located over a second source/drain region and a second adjacent end of the channel region. A control gate extends over both floating gate electrodes and a centrally located portion of the channel region. The floating gate electrodes are independently programmed and independently read, thereby enabling the NVM transistor to effectively store 2-bits of data.
摘要翻译：提供具有一对隔离浮栅电极的2位非易失性存储器（NVM）晶体管。一个浮栅电极位于第一源极/漏极区域和沟道区域的第一相邻端之间。另一个浮栅电极位于沟道区的第二源/漏区和第二相邻端之上。控制门在两个浮栅电极和沟道区的中心定位部分之间延伸。浮栅电极被独立编程并独立读取，从而使NVM晶体管有效地存储2位数据。

44. 发明申请

US20010021126A1 EEPROM array using 2 bit non-volatile memory cells and method of implementing same 审中-公开
标题翻译：使用2位非易失性存储单元的EEPROM阵列及其实现方法
公开(公告)号：US20010021126A1
公开(公告)日：2001-09-13
申请号：US09854228
申请日：2001-05-10
申请人： Tower Semiconductor Ltd.
发明人： Yoav Lavi , Ishai Nachumovsky
IPC分类号： G11C011/34
CPC分类号： G11C16/0475 , G11C16/24 , H01L27/11519 , H01L27/11521 , H01L29/7887
摘要： An electrically erasable programmable read only memory block is provided which includes a plurality of rows of 2-bit non-volatile memory cells. Each of the memory cells has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. Each pair of adjacent memory cells in each row are coupled to share a common diffusion bit line. A plurality of metal bit lines are coupled to the diffusion bit lines through high voltage select transistors. In one embodiment, there are half as many metal bit lines as diffusion bit lines.
摘要翻译：提供了一种电可擦除可编程只读存储器块，其包括多行2位非易失性存储器单元。每个存储单元具有用于存储第一位的第一电荷捕获区和用于存储第二位的第二电荷捕获区。每行中的每对相邻存储单元被耦合以共享公共扩散位线。多个金属位线通过高电压选择晶体管耦合到扩散位线。在一个实施例中，存在与扩散位线一样多的金属位线。

45. 发明授权

US6157570A Program/erase endurance of EEPROM memory cells 有权
标题翻译： EEPROM存储单元的编程/擦除耐久性
公开(公告)号：US6157570A
公开(公告)日：2000-12-05
申请号：US243973
申请日：1999-02-04
申请人： Ishai Nachumovsky
发明人： Ishai Nachumovsky
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34 , H01L27/115
CPC分类号： G11C16/3495 , G11C11/5671 , G11C16/0475 , G11C16/349 , H01L27/115
摘要： A circuit and method increases the endurance of memory cells in a memory array by decreasing the number of times a memory cell is programmed or erased. A bit-wise program/erase controller coupled to the memory array modifies the erasing and programming of multi-bit data words by erasing only those memory cells which must be erased and programming only those memory cells which must be programmed. Specifically, the bit-wise program/erase controller compares a new data word, which will be written into the memory array at a write address, with the current data word at the write address. The memory cells at the write address are categorized into a first subset and a second subset. The first subset of memory cells are currently in a programmed state but must be erased because the corresponding bit of the new data word is at an erased logic level. The second subset of memory cells are currently in an erased state but must be programmed because the corresponding bit of the new data word is at a programmed logic level. Bit-wise program/erase controller erases only the first subset of memory cells and programs only the second subset of memory cells. Thus, over multiple writes into the memory array, the number times each memory cell is erased or programmed is reduced resulting in greater endurance of the memory cells.
摘要翻译：电路和方法通过减少存储器单元被编程或擦除的次数来增加存储器阵列中存储单元的耐久性。耦合到存储器阵列的逐位程序/擦除控制器通过仅擦除必须擦除的那些存储器单元并且仅编程那些必须被编程的存储器单元来修改多位数据字的擦除和编程。具体来说，逐位编程/擦除控制器将在写入地址处将写入存储器阵列的新数据字与写入地址处的当前数据字进行比较。写地址处的存储单元被分类为第一子集和第二子集。存储器单元的第一子集当前处于编程状态，但必须被擦除，因为新数据字的相应位处于擦除的逻辑电平。存储器单元的第二子集当前处于擦除状态，但必须被编程，因为新数据字的相应位处于编程逻辑电平。逐位程序/擦除控制器仅擦除存储器单元的第一个子集，仅擦除存储器单元的第二个子集。因此，在对存储器阵列的多次写入中，每个存储单元被擦除或编程的次数减少，导致存储器单元的更大的耐久性。

46. 发明授权

US5691247A Method for depositing a flow fill layer on an integrated circuit wafer 失效
标题翻译：在集成电路晶片上沉积流动填充层的方法
公开(公告)号：US5691247A
公开(公告)日：1997-11-25
申请号：US769853
申请日：1996-12-19
申请人： Zmira Lavie , Aviad Roth , Jeff Levy , Itzhak Edrei
发明人： Zmira Lavie , Aviad Roth , Jeff Levy , Itzhak Edrei
IPC分类号： H01L21/316 , A01L21/316
CPC分类号： H01L21/31051 , H01L21/02126 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/02337 , Y10S438/902
摘要： An improved method for depositing the cap layer of a flow fill layer of an integrated circuit. The cap layer is deposited in at least two steps, instead of all at once.
摘要翻译：一种用于沉积集成电路的流动填充层的盖层的改进方法。盖层以至少两个步骤沉积，而不是全部沉积。

47. 发明公开

US20240063038A1 DETECTION OF A POSITION OF A WAFER WITHIN A TRANSFER ROBOT VACUUM CHAMBER 审中-公开
公开(公告)号：US20240063038A1
公开(公告)日：2024-02-22
申请号：US17821175
申请日：2022-08-21
申请人： Tower Semiconductor Ltd.
发明人： Slava Superfine , Yaniv Malachy , Dany Trabelsi
IPC分类号： H01L21/67 , G01B11/27
CPC分类号： H01L21/67259 , G01B11/272
摘要： A location detection system for detecting a location of a wafer within a transfer robot vacuum chamber (TRVC), the detection system may include (i) an illumination unit that is configured to direct a transmitted radiation pattern through a transparent window of the TRVC and towards one or more TRVS reflecting elements located below an upper side of a wafer holding element of the transfer robot; wherein the illumination unit is located outside the TRVC; (ii) a sensing unit that is configured to generate one or more detection signals indicative of a received radiation pattern that is reflected from the one or more TRVS reflecting elements; and (iii) a location processing circuit that is configured to detect a location of the wafer based on the one or more detection signals.

48. 发明公开

US20230345149A1 ROBUST ANALOG COUNTER 审中-公开
公开(公告)号：US20230345149A1
公开(公告)日：2023-10-26
申请号：US17660830
申请日：2022-04-26
申请人： Tower Semiconductor Ltd.
发明人： Raz Reshef , Dmitry Dain
IPC分类号： H04N5/369 , H04N5/378
CPC分类号： H04N5/378 , H04N5/3696
摘要： A robust analog counter that may include an output capacitor having a first capacitance, and a charging unit (CU) that is configured to determine that an event to be counted occurred, and charge the output capacitor at a first current and during a output capacitor charging period, wherein a duration of the output capacitor charging period is proportional to the first capacitance, thereby increasing an output voltage of the output capacitor by a voltage quote that is indifferent to at least one out of process variation, temperature or power supply voltage value.

49. 发明申请

US20230042154A1 WAVELENGTH SELECTIVE RADIATION SENSOR 有权
公开(公告)号：US20230042154A1
公开(公告)日：2023-02-09
申请号：US17444562
申请日：2021-08-05
申请人： Tower Semiconductor Ltd.
发明人： Amos Fenigstein
IPC分类号： G01T1/24 , H01L27/144
摘要： There may be provided a radiation sensor, that may include multiple semiconductor regions that form a sensing PN junction and a draining PN junction that is located below the sensing PN junction; a bias circuit that is configured to (i) bias the sensing PN junction to maintain a sensing PN junction depletion region of a fixed size during a first sensing period and during a second sensing period, and (i) bias the draining PN junction to form a draining PN junction depletion region of a first size during the first sensing period and of a second size during the second sensing period; and an output circuit that is configured to generate a first output signal that represent sensed radiation out of radiation that impinged on the radiation sensor during the first sensing period, and to generate a second output signal that represent sensed radiation out of radiation impinged on the radiation sensor during the second sensing period.

50. 发明授权

US11522079B2 Electrostatically controlled gallium nitride based sensor and method of operating same 有权
公开(公告)号：US11522079B2
公开(公告)日：2022-12-06
申请号：US16654977
申请日：2019-10-16
申请人： Tower Semiconductor Ltd.
发明人： Yakov Roizin , Victor Kairys , Ruth Shima-edelstein
IPC分类号： H01L29/778 , H01L29/205 , H01L29/417 , H01L29/51 , H01L29/423 , H01L23/34 , H01L31/113 , H01L29/82 , H01L31/0304 , H01L31/024 , H01L29/66 , H01L21/02 , H01L29/40 , H01L31/18 , G01N27/22 , G01R33/02 , G01J1/42 , H01L29/20 , H01L21/265 , H01L21/285 , H01L21/266
摘要： An electrostatically controlled sensor includes a GaN/AlGaN heterostructure having a 2DEG channel in the GaN layer. Source and drain contacts are electrically coupled to the 2DEG channel through the AlGaN layer. A gate dielectric is formed over the AlGaN layer, and gate electrodes are formed over the gate dielectric, wherein each gate electrode extends substantially entirely between the source and drain contacts, wherein the gate electrodes are separated by one or more gaps (which also extend substantially entirely between the source and drain contacts). Each of the one or more gaps defines a corresponding sensing area between the gate electrodes for receiving an external influence. A bias voltage is applied to the gate electrodes, such that regions of the 2DEG channel below the gate electrodes are completely depleted, and regions of the 2DEG channel below the one or more gaps in the direction from source to drain are partially depleted.

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