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41. 发明授权

US08242510B2 Monolithic integration of gallium nitride and silicon devices and circuits, structure and method 有权
标题翻译：氮化镓和硅器件与电路的整体集成，结构和方法
公开(公告)号：US08242510B2
公开(公告)日：2012-08-14
申请号：US12946669
申请日：2010-11-15
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L29/15
CPC分类号： H01L29/7787 , H01L21/0242 , H01L21/0245 , H01L21/0254 , H01L21/02658 , H01L21/76281 , H01L21/8258 , H01L27/085 , H01L29/2003 , H01L29/66462
摘要： A structure and method for a semiconductor device includes a silicon device layer and a gallium nitride (GaN) device layer. In an embodiment, the silicon device layer and the GaN device layer have upper surfaces which are coplanar with each other. In another embodiment, the GaN device layer does not directly underlie the silicon device layer, and the silicon device layer does not directly underlie the GaN device layer. The semiconductor device can further include a silicon-based semiconductor device formed on and/or within the silicon device layer, and a nitride-based semiconductor device formed on and/or within the GaN device layer. The GaN device layer can include a plurality of layers which can be formed as conformal blanket layers and then planarized, or which can be selectively formed then planarized.
摘要翻译：半导体器件的结构和方法包括硅器件层和氮化镓（GaN）器件层。在一个实施例中，硅器件层和GaN器件层具有彼此共面的上表面。在另一个实施例中，GaN器件层不直接位于硅器件层之下，并且硅器件层不直接位于GaN器件层的下面。半导体器件还可以包括形成在硅器件层上和/或内部的硅基半导体器件，以及形成在GaN器件层上和/或内部的氮化物基半导体器件。 GaN器件层可以包括可以形成为保形覆盖层然后平坦化的多个层，或者可以选择性地形成，然后进行平面化。

42. 发明申请

US20120200272A1 SHUNT REGULATOR FOR HIGH VOLTAGE OUTPUT USING INDIRECT OUTPUT VOLTAGE SENSING 审中-公开
标题翻译：使用间接输出电压感测的高压输出调节器
公开(公告)号：US20120200272A1
公开(公告)日：2012-08-09
申请号：US13332933
申请日：2011-12-21
申请人： Andrew Paul Le Fevre , Neil E. Robinson
发明人： Andrew Paul Le Fevre , Neil E. Robinson
IPC分类号： G05F1/10
CPC分类号： G05F1/613
摘要： Embodiments disclosed herein provide for a voltage regulator having one or more Zener diodes coupled in series between an output voltage and system ground. The one or more Zener diodes are in a reverse biased configuration. A transistor is coupled in series with the one or more Zener diodes between the one or more Zener diodes and system ground. A control circuit is coupled to the transistor and configured to adjust the transistor to control a voltage level of the output voltage. The control circuit is configured such that transistor is adjusted substantially independent of values of the one or more Zener diodes.
摘要翻译：本文公开的实施例提供了具有在输出电压和系统接地之间串联耦合的一个或多个齐纳二极管的电压调节器。一个或多个齐纳二极管处于反向偏置配置。晶体管与一个或多个齐纳二极管和系统接地之间的一个或多个齐纳二极管串联耦合。控制电路耦合到晶体管并被配置为调节晶体管以控制输出电压的电压电平。控制电路被配置为使晶体管基本上独立于一个或多个齐纳二极管的值进行调节。

43. 发明授权

US08232782B2 System and method for equalizing the small signal response of variable phase voltage regulators 有权
标题翻译：用于均衡可变相电压调节器的小信号响应的系统和方法
公开(公告)号：US08232782B2
公开(公告)日：2012-07-31
申请号：US12761914
申请日：2010-04-16
申请人： M. Jason Houston , Bogdan M. Duduman , Weihong Qiu
发明人： M. Jason Houston , Bogdan M. Duduman , Weihong Qiu
IPC分类号： G05F1/575 , G05F1/656
CPC分类号： H04L25/0272 , H02M3/1584 , H04L25/4902
摘要： A control circuit for a variable phase voltage regulator comprises an error amplifier to generate a difference signal based on a difference between a reference voltage and a signal representative of a voltage at an output node of the variable phase voltage regulator. The control circuit also comprises a variable phase compensator to amplify the difference signal to produce a modified difference signal to compensate for effects of varying the number of active phases in the variable phase voltage regulator, wherein the amplification is proportional to a ratio of total number of phases in the variable phase voltage regulator to number of active phases in the variable phase voltage regulator.
摘要翻译：用于可变相位调压器的控制电路包括误差放大器，用于基于参考电压和表示可变相位电压调节器的输出节点处的电压的信号之间的差产生差分信号。控制电路还包括可变相位补偿器，用于放大差分信号以产生修改的差分信号，以补偿在可变相电压调节器中改变有效相数量的影响，其中放大与总数可变相电压调节器中的相位可变相电压调节器中的有效相数。

44. 发明授权

US08232137B2 Heat conduction for chip stacks and 3-D circuits 失效
标题翻译：芯片堆叠和3-D电路的导热
公开(公告)号：US08232137B2
公开(公告)日：2012-07-31
申请号：US12773275
申请日：2010-05-04
申请人： Stephen Joseph Gaul , Francois Hebert
发明人： Stephen Joseph Gaul , Francois Hebert
IPC分类号： H01L21/00
CPC分类号： H01L23/3732 , H01L23/3677 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/14 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/06181 , H01L2224/06515 , H01L2224/1403 , H01L2224/14515 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/1305 , H01L2924/13062 , H01L2924/14 , H01L2924/00
摘要： A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.
摘要翻译：半导体器件组件和方法可以包括单个半导体层或层叠的半导体层，例如半导体晶片或晶片部分（半导体晶片）。在每个半导体层上，通过其形成的金刚石层可有助于散热和散热。金刚石层可以包括半导体层背面的第一部分和垂直延伸到半导体层中的一个或多个第二部分，例如完全穿过半导体层。然后可以对金刚石层进行热接触以将热量从一个或多个半导体层导出。可以通过金刚石层形成导电通孔，以提供信号路由和散热能力。

45. 发明申请

US20120188461A1 DATA LOOK AHEAD TO REDUCE POWER CONSUMPTION 审中-公开
标题翻译：数据看起来要减少耗电量
公开(公告)号：US20120188461A1
公开(公告)日：2012-07-26
申请号：US13437319
申请日：2012-04-02
申请人： Dimitrios Katsis , Barry Concklin
发明人： Dimitrios Katsis , Barry Concklin
IPC分类号： H04N9/64
CPC分类号： H03M1/002 , H03M1/687
摘要： Portions of a digital signal are buffered prior to being provided to a sub-system (e.g., a segmented DAC of a LDD) that is responsive to the digital signal. While being buffered, there is a determination, based on the buffered portions of the digital signal, of when one or more portions of the sub-system and/or another sub-system can be switched from a first state to a second state, where the second state results in less power dissipation than the first state. Based on results of the determination(s), the state of one or more portions of the sub-system and/or another sub-system is/are selectively switched from the first state to the second state, or vice versa. Eventually, the portions of the digital signal are provided to the sub-system so that the sub-system can respond to the portions of the digital signal.
摘要翻译：在将数字信号提供给响应于数字信号的子系统（例如，LDD的分段DAC）之前，缓冲数字信号的部分。当被缓冲时，基于数字信号的缓冲部分确定当子系统和/或另一个子系统的一个或多个部分可以从第一状态切换到第二状态时，其中第二状态导致比第一状态更少的功率耗散。基于确定的结果，子系统和/或另一子系统的一个或多个部分的状态被选择性地从第一状态切换到第二状态，反之亦然。最终，将数字信号的部分提供给子系统，使得子系统可以对数字信号的部分做出响应。

46. 发明申请

US20120171817A1 SINGLE DIE OUTPUT POWER STAGE USING TRENCH-GATE LOW-SIDE AND LDMOS HIGH-SIDE MOSFETS, STRUCTURE AND METHOD 有权
标题翻译：单晶硅输出功率级使用TRENCH-GATE低边和LDMOS高边MOSFET，结构和方法
公开(公告)号：US20120171817A1
公开(公告)日：2012-07-05
申请号：US13415384
申请日：2012-03-08
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L21/50
CPC分类号： H01L27/088 , H01L21/26513 , H01L21/823437 , H01L21/823487 , H01L23/535 , H01L23/62 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66712 , H01L29/66734 , H01L29/7802 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7816 , H01L29/7835 , H01L2224/48137 , H01L2224/48247 , H01L2224/49171 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/1461 , H01L2924/30107 , H01L2924/3025 , H02M7/003 , H01L2924/00
摘要： A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.
摘要翻译：电压转换器包括具有可以形成在单个管芯（“PowerDie”）上的高侧器件和低侧器件的输出电路。高侧器件可以包括横向扩散金属氧化物半导体（LDMOS），而低侧器件可以包括沟槽栅极垂直扩散金属氧化物半导体（VDMOS）。电压转换器还可以包括在不同管芯上的控制器电路，其可以电耦合到输出电路并与输出电路共同封装。

47. 发明申请

US20120153861A1 SYSTEMS AND METHODS FOR DYNAMIC POWER MANAGEMENT FOR USE WITH A VIDEO DISPLAY DEVICE 失效
标题翻译：用于动态显示设备的动态电源管理的系统和方法
公开(公告)号：US20120153861A1
公开(公告)日：2012-06-21
申请号：US13013700
申请日：2011-01-25
申请人： Dimitrios Katsis , Barry Concklin , Daryl Chamberlin , Peter J. Mole
发明人： Dimitrios Katsis , Barry Concklin , Daryl Chamberlin , Peter J. Mole
IPC分类号： H05B37/02
CPC分类号： G09G3/025 , G09G5/10 , G09G2320/043 , G09G2330/021 , G09G2360/145
摘要： Embodiments of the present invention relate to methods and circuits for use with a system including a light emitting element (e.g., a laser diode or light emitting diode) that is driven by a current produced by a current output digital-to-analog converter (DAC), wherein the light emitting element or the DAC is powered by a supply voltage produced by a voltage supply. In accordance with an embodiment, a measure indicative of a voltage at an output of the DAC is obtained, wherein the voltage at the output of the DAC is indicative of a voltage headroom available for the DAC. The measure indicative of the voltage at the output of the DAC is compared to one or more predetermined references, and the supply voltage is controlled based on the comparison(s).
摘要翻译：本发明的实施例涉及用于包括由电流输出数模转换器（DAC）产生的电流驱动的发光元件（例如，激光二极管或发光二极管）的系统的方法和电路），其中发光元件或DAC由电压源产生的电源电压供电。根据实施例，获得指示DAC输出处的电压的量度，其中DAC的输出处的电压表示可用于DAC的电压余量。将表示DAC输出端的电压的量度与一个或多个预定参考值相比较，并且基于比较来控制电源电压。

48. 发明授权

US08203359B2 System and method for open loop modulation to detect narrow PWM pulse 有权
标题翻译：用于开环调制的系统和方法，用于检测窄脉宽
公开(公告)号：US08203359B2
公开(公告)日：2012-06-19
申请号：US13034416
申请日：2011-02-24
申请人： Noel B. Dequina , M. Jason Houston
发明人： Noel B. Dequina , M. Jason Houston
IPC分类号： H03K19/0175
CPC分类号： H02M3/158 , H02M3/156 , H02M2001/0003
摘要： An open loop modulation network for a voltage regulator including a latch network, an output sense network, a timing network, and pulse control logic. The latch network latches assertion of a pulse control signal and provides a corresponding latched control pulse indication. The output sense network detects initiation of an output pulse and provides a corresponding output pulse indication. The timing network initiates a delay period in response to the output pulse indication and resets the latched control pulse indication after expiration of the delay period. The pulse control logic terminates the output pulse after the latched control pulse indication is reset and the pulse control signal is negated, whichever occurs last. Very narrow input pulses are detected and either a minimum output pulse is generated or the output pulse is based on the pulse control signal.
摘要翻译：一种用于电压调节器的开环调制网络，包括锁存网络，输出检测网络，定时网络和脉冲控制逻辑。锁存网络锁存脉冲控制信号的断言并提供对应的锁存控制脉冲指示。输出检测网络检测输出脉冲的启动并提供相应的输出脉冲指示。定时网络响应于输出脉冲指示启动延迟时段，并且在延迟时间期满之后复位锁存的控制脉冲指示。在锁存的控制脉冲指示被复位并且脉冲控制信号被否定之后，脉冲控制逻辑终止输出脉冲，以最后发生者为准。检测到非常窄的输入脉冲，并且产生最小输出脉冲，或者输出脉冲基于脉冲控制信号。

49. 发明授权

US08203354B2 System for testing electronic components 失效
标题翻译：电子元件测试系统
公开(公告)号：US08203354B2
公开(公告)日：2012-06-19
申请号：US12688903
申请日：2010-01-17
申请人： Ryan B. Roderick , Ronald D. Kimmel
发明人： Ryan B. Roderick , Ronald D. Kimmel
IPC分类号： G01R31/00
CPC分类号： H05K1/0268 , G01R1/0466 , H05K1/141 , H05K2201/09072 , H05K2201/10189 , H05K2203/162
摘要： An improved efficiency system for testing electronic components in a motherboard/daughterboard assembly in which the daughterboard is mounted in spaced parallel relationship the to motherboard includes one or more device-under-test socket sub-assemblies having a test socket thereon for receiving a device-under-test and a connector component for disengagable connection to a complementary connector component on the daughterboard with the socket sub-assembly effecting interengagement of the complementary connector component on the daughterboard via an opening in the motherboard to allow ready access to the test socket for temporary installation, testing, and removal of a device-under-test.
摘要翻译：用于测试母板/子板组件中的电子部件的改进的效率系统，其中子板以与母板隔开的平行关系安装，包括一个或多个测试用插座子组件，其中具有用于接收设备 - 未测试和用于与子板上的互补连接器部件的可脱离连接的连接器部件，其中插座子组件通过主板中的开口实现子板上的互补连接器部件的相互接合，以允许准备对测试插座进行临时安装，测试和删除被测设备。

50. 发明授权

US08194800B2 Reducing equalizer error propagation with a low complexity soft output viterbi decoder 失效
标题翻译：降低均衡器误差传播与低复杂度软输出维特比解码器
公开(公告)号：US08194800B2
公开(公告)日：2012-06-05
申请号：US12758670
申请日：2010-04-12
申请人： Jin Hong Kim
发明人： Jin Hong Kim
IPC分类号： H04L27/06 , H04M13/03
CPC分类号： H03M13/4169 , H03M13/41 , H03M13/6331
摘要： Novel systems and methods are described in which performance of equalizers can be improved by reducing the effects of error propagation in equalizers that use a Viterbi Decoder. Systems and methods of symbol correction in prediction decision feedback equalization architectures are described including systems and methods that include an enhanced Viterbi decoder and novel methods of symbol correction to obtain better system performance. The use of a blending algorithm is described to reduce errors in symbol decoding. Histories of deep trace back depth symbols can be maintained to enable more accurate decisions. Systems and methods described can provide advantage in the feedback path of adaptive equalizers in trellis decoders. The invention provides novel techniques for improving the performance of equalizers by reducing the effects of error propagation in equalizers that use a Viterbi Decoder.
摘要翻译：描述了新颖的系统和方法，其中可以通过减少使用维特比解码器的均衡器中的误差传播的影响来改善均衡器的性能。描述了预测判决反馈均衡架构中的符号校正的系统和方法，其包括包括增强维特比解码器和符号校正的新颖方法以获得更好的系统性能的系统和方法。描述使用混合算法来减少符号解码中的错误。可以维护深回溯深度符号的历史，以实现更准确的决策。所描述的系统和方法可以在网格解码器中的自适应均衡器的反馈路径中提供优点。本发明提供了通过减少使用维特比解码器的均衡器中的误差传播的影响来提高均衡器的性能的新技术。

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