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31. 发明授权

US5118974A Tristate circuits with fast and slow OE signals 失效
标题翻译：具有快速和慢速OE信号的三态电路
公开(公告)号：US5118974A
公开(公告)日：1992-06-02
申请号：US555718
申请日：1990-07-19
申请人： Roy L. Yarbrough , Duane G. Quiet
发明人： Roy L. Yarbrough , Duane G. Quiet
IPC分类号： H03K19/013 , H03K19/082
CPC分类号： H03K19/0136 , H03K19/0826
摘要： A FAST OE signal circuit generates FAST OE signals of high and low potential levels. A SLOW OE signal circuit generates SLOW OE signals corresponding to FAST OE signals. The SLOW OE signals have the same high or low potential level as the corresponding FAST OE signals and occur a specified time delay after the corresponding FAST OE signals. A tristate output buffer circuit operates in the bistate mode when enabled by high potential level OE signals for transmitting binary data signals, and operates in a high Z tristate mode when disabled by low potential level OE signals. The FAST OE signal circuit and SLOW OE signal circuit ae coupled in parallel to the tristate output buffer circuit for enabling and disabling the tristate output buffer circuit. The FAST and SLOW OE signals in combination skew the enable time relative to the disable time. The enable times tpZH and tpZL are substantailly longer than the disable times tpHZ and tpLZ, introducing "temporal" separation between active tristate output devices on a common bus to reduce bus contention. A DC Miller killer circuit is coupled to the pulldown transistor element of the tristate output buffer circuit for turning off and holding off the pulldown transistor element in response to high potential level DCMK signals. A DCMK signal circuit generates DCMK signals corresponding to inverted FAST OE signals. A DCMK signal enhancer circuit provides transient enhancement of high potential level DCMK signals in response to corresponding low potential level FAST and SLOW OE signals.
摘要翻译： FAST OE信号电路产生高电平和低电平电平的FAST OE信号。 SLOW OE信号电路产生对应于FAST OE信号的SLOW OE信号。 SLOW OE信号与相应的FAST OE信号具有相同的高电平或低电平电平，并在相应的FAST OE信号后发生指定的时间延迟。三态输出缓冲器电路在双通道模式下工作，当由高电位电平OE信号用于发送二进制数据信号时工作，并且在由低电位OE信号禁止时以高Z三态模式工作。 FAST OE信号电路和SLOW OE信号电路并联耦合到三态输出缓冲电路，用于启用和禁用三态输出缓冲电路。 FAST和SLOW OE信号组合使相对于禁用时间的使能时间偏移。使能时间tpZH和tpZL比禁用时间tpHZ和tpLZ实质上长，引入公共总线上的有效三态输出设备之间的“时间”间隔，以减少总线争用。 DC Miller杀伤电路耦合到三态输出缓冲器电路的下拉晶体管元件，用于响应于高电位级别的DCMK信号而关断和保持下拉晶体管元件。 DCMK信号电路产生对应于反向FAST OE信号的DCMK信号。 DCMK信号增强器电路响应于相应的低电位FAST和SLOW OE信号，提供高电位电平DCMK信号的瞬态增强。

32. 发明授权

US4965651A CMOS logic array layout 失效
标题翻译： CMOS逻辑阵列布局
公开(公告)号：US4965651A
公开(公告)日：1990-10-23
申请号：US330942
申请日：1989-03-23
申请人： Karl Wagner
发明人： Karl Wagner
IPC分类号： H01L21/822 , H01L21/82 , H01L27/02 , H01L27/04 , H01L27/082 , H01L27/092 , H03K19/082 , H03K19/0948 , H03K19/096
CPC分类号： H03K19/0963 , H01L27/0207 , H01L27/0826 , H01L27/092 , H01L2924/0002
摘要： An integrated logic circuit with complementary transistors which is constructed from cells which form reproductions of logic equations, in which each cell has at least three transistors arranged one next to the other in a row and three complementary transistors arranged one next to the other. Series arrangements of transistors or transistor circuits in one row corrugated to parallel arrangements of transistors or transistor circuits in the other row. This arrangement results in compact layouts which are easy to design with computer assistance. The arrangement is particularly useful for MSI and LSI circuits.
摘要翻译：具有互补晶体管的集成逻辑电路，其由形成逻辑方程的复制的单元构成，其中每个单元具有至少三个彼此排列成一列的三个晶体管，以及彼此排列的三个互补晶体管。一行中的晶体管或晶体管电路的串联布置在另一排中波导到晶体管或晶体管电路的并联布置。这种布置导致紧凑的布局，其易于利用计算机辅助来设计。该装置对于MSI和LSI电路特别有用。

33. 发明授权

US4953070A Method for transverse-current-free operation of a push-pull circuit, and apparatus for performing the method 失效
标题翻译：用于推挽电路的无横向无电流操作的方法，以及用于执行该方法的装置
公开(公告)号：US4953070A
公开(公告)日：1990-08-28
申请号：US256745
申请日：1988-10-12
申请人： Michael Lenz
发明人： Michael Lenz
IPC分类号： H03K17/16 , H02M1/00 , H02M1/38 , H02M7/538 , H03K17/66 , H03K19/082 , H03K19/088
CPC分类号： H02M1/38 , H02M7/53803 , H03K17/667
摘要： A method for transverse-current-free operation of a push-pull circuit configuration having two output transistor arrays of complementary types with output circuits interconnected in series, and a trigger circuit triggering the output transistor arrays with two push-pull signals being derived from one input signal and having mutually associated edges consecutively following one another with temporal separation, and detecting output currents of the output transistor arrays. The method includes releasing the particular triggering push-pull signal for an output transistor array without delay whenever the output current of the complementary output transistor arrays drops below a predetermined positive minimum value. An apparatus for performing the method includes comparators associated with the output transistor arrays for detecting the predetermined minimum output currents. The comparators each have an output cross-coupled directly to the first input of a respective logical linkage element. The second input of one of the logical linkage elements receives the input signal and the second input of the other of the logical linkage elements receives an inverted input signal.
摘要翻译：一种具有互补类型的两个输出晶体管阵列和串联互连的输出电路的推挽电路配置的横向无电流操作的方法，以及由两个推挽信号触发输出晶体管阵列的触发电路，该触发电路从一个输入信号并且具有相互相关联的边缘，并且随时间间隔地彼此相继地连接，并且检测输出晶体管阵列的输出电流。该方法包括当互补输出晶体管阵列的输出电流下降到预定的正最小值以下时，无延迟释放用于输出晶体管阵列的特定触发推挽信号。用于执行该方法的装置包括与用于检测预定最小输出电流的输出晶体管阵列相关联的比较器。比较器各自具有直接与相应的逻辑连接元件的第一输入交叉耦合的输出。逻辑联动元件之一的第二输入接收输入信号，另一个逻辑连接元件的第二输入接收反相输入信号。

34. 发明授权

US4857776A True TTL output translator-driver with true ECL tri-state control 失效
标题翻译：真正的TTL输出转换器驱动，具有真正的ECL三态控制
公开(公告)号：US4857776A
公开(公告)日：1989-08-15
申请号：US123093
申请日：1987-11-20
申请人： Aurangzeb K. Khan
发明人： Aurangzeb K. Khan
IPC分类号： H03K19/013 , H03K19/0175 , H03K19/018 , H03K19/082
CPC分类号： H03K19/01812 , H03K19/013 , H03K19/0826
摘要： The present invention provdes a circuit for driving a TTL bus from an ECL circuit. The circuit of the present invention speeds up the "tri-state" to "active" transition by eliminating the need to pass the tri-state signal through a translator and buffer. A tri-state control circuit accepts true ECL input directly, thus eliminating the delay, power and density "cost" of the translator and buffer circuits. This circuit further improves the delay performance of tri-state/active transitions by restricting device saturation to low levels.

35. 发明授权

US4804868A BiMOS logical circuit 失效
标题翻译： BiMOS逻辑电路
公开(公告)号：US4804868A
公开(公告)日：1989-02-14
申请号：US106362
申请日：1987-10-09
申请人： Masami Masuda , Takayuki Kawaguchi , Yasumitsu Nozawa
发明人： Masami Masuda , Takayuki Kawaguchi , Yasumitsu Nozawa
IPC分类号： H01L21/8249 , H01L21/8222 , H01L21/8248 , H01L27/06 , H03K17/56 , H03K19/08 , H03K19/0944 , H03K19/096 , H03K19/01 , H03K19/003 , H03K19/082 , H03K19/094
CPC分类号： H03K19/09448 , H03K19/0963
摘要： This invention is a BiMOS logical circuit that provides a suitable output level with a limited number of components. The intermediate node of a PMOS transistor and an NMOS transistor is connected to the base of a bipolar transistor to control output voltage. The NMOS transistor is connected between the output terminal and the power source, and an output voltage approximately equal to the power supply voltage is obtained at the output terminal.
摘要翻译：本发明是一种BiMOS逻辑电路，其提供具有有限数量的组件的合适的输出电平。 PMOS晶体管的中间节点和NMOS晶体管连接到双极晶体管的基极以控制输出电压。 NMOS晶体管连接在输出端子与电源之间，在输出端子处获得大致等于电源电压的输出电压。

36. 发明授权

US4740718A Bi-CMOS logic circuit 失效
标题翻译：双CMOS逻辑电路
公开(公告)号：US4740718A
公开(公告)日：1988-04-26
申请号：US31923
申请日：1987-03-30
申请人： Masataka Matsui
发明人： Masataka Matsui
IPC分类号： H01L21/8249 , H01L27/06 , H03K19/013 , H03K19/08 , H03K19/0944 , H03K19/01 , H03K19/003 , H03K19/082 , H03K19/094
CPC分类号： H03K19/09448 , H03K19/0136
摘要： A Bi-CMOS logic circuit having a totem pole-type output buffer, a CMOS logic circuit, and a latch circuit. The output buffer comprises a pull-up NPN bipolar transistor and a pull-down NPN bipolar transistor. The CMOS logic circuit controls the base current of the pull-up NPN bipolar transistor. The latch circuit controls the base current of the pull-down NPN bipolar transistor. The latch circuit includes at least two N-type MOSFETs. The first MOSFET has a gate coupled to the input terminal of the CMOS logic circuit, a drain connected to the node of the first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor. The second MOSFET has a drain coupled to the input terminal of the CMOS logic circuit, a gate connected to the node of the first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor.
摘要翻译：具有图腾柱型输出缓冲器，CMOS逻辑电路和锁存电路的Bi-CMOS逻辑电路。输出缓冲器包括上拉NPN双极晶体管和下拉NPN双极晶体管。 CMOS逻辑电路控制上拉NPN双极晶体管的基极电流。锁存电路控制下拉NPN双极晶体管的基极电流。锁存电路包括至少两个N型MOSFET。第一MOSFET具有耦合到CMOS逻辑电路的输入端的栅极，连接到第一和第二NPN双极晶体管的节点的漏极和耦合到所述第二NPN双极晶体管的基极的源极。第二MOSFET具有耦合到CMOS逻辑电路的输入端的漏极，连接到第一和第二NPN双极晶体管的节点的栅极以及耦合到所述第二NPN双极晶体管的基极的源极。

37. 发明授权

US4737663A Current source arrangement for three-level emitter-coupled logic and four-level current mode logic 失效
标题翻译：三电平发射极耦合逻辑和四电平电流模式逻辑的电流源装置
公开(公告)号：US4737663A
公开(公告)日：1988-04-12
申请号：US585315
申请日：1984-03-01
申请人： Hemmige D. Varadarajan
发明人： Hemmige D. Varadarajan
IPC分类号： H03K19/082 , H03K19/086
CPC分类号： H03K19/0823 , H03K19/0866
摘要： Three-level ECL or four-level CML are feasible when a low drop current source is incorporated in the series-gated arrangement. The low drop current source consumes less than one-tenth of the voltage span between V.sub.CC and ground. A greater portion of the voltage span between V.sub.CC and ground, up to 4 volts, is therefore reserved for the three ECL levels or four CML levels of logic. Conventional power supplies are utilized yet the number of logic functions is increased.
摘要翻译：当将低压电流源并入串联布置时，三电平ECL或四电平CML是可行的。低压降电流源消耗的电压跨度在VCC和地之间的十分之一。因此，VCC和地之间的电压跨度的较大部分高达4伏特，因此保留用于三个ECL电平或四个CML逻辑电平。利用传统的电源，增加了逻辑功能的数量。

38. 发明授权

US4641047A Complex direct coupled transistor logic 失效
标题翻译：复合直接耦合晶体管逻辑
公开(公告)号：US4641047A
公开(公告)日：1987-02-03
申请号：US627312
申请日：1984-07-02
申请人： Mark S. Birrittella
发明人： Mark S. Birrittella
IPC分类号： H03K19/082 , H03K19/091 , H01L27/04
CPC分类号： H03K19/082 , H03K19/091
摘要： A logic circuit is provided having increased flexibility, increased package density over I2L circuits and improved noise immunity over ISL circuits. A first NPN multi-collector transistor has its collectors coupled wherein each provide an output signal, and a base connected to an input terminal and to the base of a second NPN transistor. The emitter of the second transistor is coupled to receive a first supply voltage, typically ground. The input terminal is coupled to a second supply voltage by a resistor. When monolithically integrated, the emitter and collector of the first and second transistor, respectively, share a common buried epitaxial layer that does not require contact with a metallization layer.
摘要翻译：提供了一种逻辑电路，其具有增加的灵活性，增加了I2L电路上的封装密度，并且提高了超过ISL电路的抗噪声能力。第一NPN多集电极晶体管具有耦合其集电极，其中每个提供输出信号，以及连接到第二NPN晶体管的输入端和基极的基极。第二晶体管的发射极被耦合以接收通常接地的第一电源电压。输入端通过电阻耦合到第二电源电压。当单片集成时，第一和第二晶体管的发射极和集电极分别共享不需要与金属化层接触的公共掩埋外延层。

39. 发明授权

US4633104A Bipolar transistor logic circuits 失效
标题翻译：双极晶体管逻辑电路
公开(公告)号：US4633104A
公开(公告)日：1986-12-30
申请号：US650649
申请日：1984-09-14
申请人： Andrew M. Mallinson
发明人： Andrew M. Mallinson
IPC分类号： H03K19/082 , H03K3/356 , H03K19/086 , H03K19/20 , H03K19/21
CPC分类号： H03K19/212 , H03K19/0866
摘要： A bipolar transistor logic circuit has a hierarchical arrangement of pairs of bipolar transistors, each pair of transistors having their emitters connected together, and the bases of at least some pairs receiving a differential input to the logic circuit. The highest level has only one pair of transistors, with their emitters connected to a constant current source. A differential output is provided on two lines, at least the collectors of the lowest level being coupled selectively to the lines. The arrangement is required to be symmetrical. In an otherwise non-symmetrical arrangement, the arrangement is made symmetrical by including dummy pairs of transistors not receiving a differential input. In performing a logical operation, the differential output, and the collector potentials of each pair of transistors start to vary in the appropriate sense. Further, there is a switch controlling the constant current source enabling the logic circuit to be driven ON and OFF so that the logic circuit starts each operation in the equilibrium condition. Hence the logic circuit is fast in operation. In one embodiment, the logic circuit also includes a latch having two parallel arms, each arm including an input transistor coupled to the hierarchical arrangement, and a switching transistor. The switching transistor collectors and bases are cross-coupled, and the emitters are connected together and to two parallel constant current sources. The output of one source is insufficient to drive the latch, but is sufficient to set the latch. The output of the other source is sufficient to drive the latch, and is connected to the switching transistors via controlled by timing means common also to the switch associated with the hierarchical arrangement.
摘要翻译：双极晶体管逻辑电路具有双极晶体管对的分层布置，每对晶体管的发射极连接在一起，并且至少一些对的基极接收到逻辑电路的差分输入。最高级只有一对晶体管，其发射极连接到恒流源。差分输出提供在两条线上，至少最下层的集电极选择性地耦合到线路。该布置需要对称。在另外非对称的布置中，通过包括未接收差分输入的晶体管的虚拟对来使布置对称。在执行逻辑运算时，每对晶体管的差分输出和集电极电位在合适的意义上开始变化。此外，存在控制恒定电流源的开关，使得逻辑电路能够被导通和截止，使得逻辑电路在平衡条件下开始每个操作。因此逻辑电路运行正常。在一个实施例中，逻辑电路还包括具有两个并联臂的锁存器，每个臂包括耦合到分级布置的输入晶体管和开关晶体管。开关晶体管集电极和基极交叉耦合，发射极连接在一起并连接到两个并联的恒流源。一个源的输出不足以驱动锁存器，但是足以设置锁存器。另一个源的输出足以驱动锁存器，并且通过与分层布置相关联的开关通用的定时装置控制而连接到开关晶体管。

40. 发明授权

US4620188A Multi-level logic circuit 失效
标题翻译：多级逻辑电路
公开(公告)号：US4620188A
公开(公告)日：1986-10-28
申请号：US408118
申请日：1982-08-13
申请人： Chanty Sengchanh
发明人： Chanty Sengchanh
IPC分类号： H03K19/20 , G06N7/04 , H03K19/082 , H04Q1/00 , H03K19/08
CPC分类号： G06N7/043 , H03K19/0823
摘要： A Multi-Level Logic Circuit is described, with the hardware of the circuit capable of being constructed to operate in a chosen base. The circuit includes at least: (a) One input level detector which can receive one or more multi-level inputs, (b) Control switching means, and (c) An output level generator delivering a single multi-level output.Various logic gates operating in any base can be derived from the generalized circuit of this invention. Basic multi-level logic gates include an (n-1) complementer, where an output of (n-1-a) is generated from a discrete input "a" where n is the base for which the circuit is constructed. A complementary maximum gate is also described in which the circuit provides the (n-1) complement of the highest logic level detected on input lines to the input level detector. Various other multi-level logic circuits can be constructed by combining the multi-level complementer, and multi-level complementary maximum gates. Circuits are also described where there are more than one input level detector or control switching means to provide binary operations on inputs to the multi-level logic circuits, e.g. addition, multiplication, in any desired base. Circuits are illustrated, constructed to operate in base 10.The multi-level logic circuit is similar to a binary circuit in that it operates on discrete logic levels. It is not an analog circuit.
摘要翻译：描述了一种多电平逻辑电路，其中电路的硬件能够被构造成在所选择的基础中运行。该电路至少包括：（a）一个输入电平检测器，其可以接收一个或多个多电平输入，（b）控制开关装置，以及（c）输出电平发生器，其提供单个多电平输出。可以从本发明的广义电路导出在任何基地中操作的各种逻辑门。基本的多电平逻辑门包括（n-1）个补码器，其中从n是构成电路的基础的离散输入“a”产生（n-1-a）的输出。还描述了互补最大门，其中电路将输入线上检测到的最高逻辑电平的（n-1）个补码提供给输入电平检测器。可以通过组合多级补码器和多级互补最大门来构建各种其他多级逻辑电路。还描述了电路，其中存在多于一个输入电平检测器或控制切换装置，以向多电平逻辑电路的输入提供二进制运算，例如，另外，在任何所需的基础上进行乘法。示出了构造为在基极10中操作的电路。多电平逻辑电路类似于二进制电路，因为它在离散逻辑电平上操作。它不是模拟电路。

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