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31. 发明授权

US5258665A AC Miller-Killer circuit for L.fwdarw.Z transitions 失效
标题翻译：用于L> Z转换的AC Miller-Killer电路
公开(公告)号：US5258665A
公开(公告)日：1993-11-02
申请号：US881540
申请日：1992-05-12
申请人： Michael G. Ward , Roy L. Yarbrough
发明人： Michael G. Ward , Roy L. Yarbrough
IPC分类号： H03K19/013 , H03K19/01 , H03K19/08
CPC分类号： H03K19/0136
摘要： A circuit to be used with tristate output buffers as a means of diverting from the output pulldown transistor control nodes Miller Current arising while the output buffer is being switched from the low-active state L to the inactive state Z. The circuit complements a DC Miller Killer circuit, relieving the latter from having to deal with this transient, and hence permitting a down-sizing of the DCMK transistor. The net effect is a significantly faster L.fwdarw.Z transition for the tristate buffer and a slightly faster Z.fwdarw.L transition, all accomplished without degrading the DC Miller Killer protection against L.fwdarw.H bus transitions.The key to the present invention is its use of the time interval between the respective, sequential switching of the enable buffer outputs, E and EB following the application of a disable signal to this enable buffer. The present invention includes circuitry which ensures that its Miller Killer transistor is conducting only during the transient associated with the L.fwdarw.Z switching. One embodiment for accomplishing this is to connect the control node of an "LZ/ACMK" transistor to the high-potential power rail through two control transistors wired in series. Then, by arranging the circuitry so that both control transistors are conducting only when E and EB are both logic-low, a situation which arises only in the midst of a transition of the output buffer into its Z state, the desired AC operation of the present Miller Killer is achieved.
摘要翻译：与三态输出缓冲器一起使用的电路作为从输出下拉晶体管控制节点转移的手段，当输出缓冲器从低电平有效状态L切换到无效状态Z时，出现的Miller电流。该电路补充了DC Miller 杀死电路，使后者不必处理这种瞬变，从而允许DCMK晶体管的尺寸减小。净效应是三态缓冲器的L> Z跃迁显着更快，并且稍微更快的Z-> L跃迁，都不会降低DC Miller Killer保护以防止L> H总线转换。本发明的关键是使用在向该使能缓冲器应用禁用信号之后，使能缓冲器输出E和EB的相应顺序切换之间的时间间隔。本发明包括确保其Miller Killer晶体管仅在与L> Z切换相关联的瞬态期间导通的电路。实现这一点的一个实施例是通过串联连接的两个控制晶体管将“LZ / ACMK”晶体管的控制节点连接到高电位电力轨。然后，通过布置电路，使得只有当E和EB都是逻辑低电平时，两个控制晶体管才导通，仅在输出缓冲器转换到其Z状态的中间出现的情况下，期望的AC操作目前Miller Killer已经实现了。

32. 发明授权

US5023478B1 COMPLEMENTARY EMITTER FOLLOWER DRIVERS 失效
标题翻译：补充发动机驱动器
公开(公告)号：US5023478B1
公开(公告)日：1993-06-01
申请号：US49307990
申请日：1990-03-13
IPC分类号： H03K19/086 , H03F1/30 , H03F3/30 , H03K17/56 , H03K17/567 , H03K17/66 , H03K19/01 , H03K19/013 , H03K19/018 , H03K19/08 , H03K19/092 , H03K19/017
CPC分类号： H03K19/013 , H03F1/308 , H03F3/3008 , H03F3/3071 , H03K17/667

33. 发明授权

US4825107B1 失效
公开(公告)号：US4825107B1
公开(公告)日：1992-08-18
申请号：US15557488
申请日：1988-02-12
申请人： FUJITSU LTD
发明人： MASAYUKI NAGANUMA , YOSHIYUKI SUEHIRO
IPC分类号： H01L21/82 , H01L21/822 , H01L23/525 , H01L27/04 , H01L27/118 , H03K3/01 , H03K19/01
CPC分类号： H01L27/11898 , H01L23/525 , H01L2924/0002 , H01L2924/00

34. 发明授权

US4804868A BiMOS logical circuit 失效
标题翻译： BiMOS逻辑电路
公开(公告)号：US4804868A
公开(公告)日：1989-02-14
申请号：US106362
申请日：1987-10-09
申请人： Masami Masuda , Takayuki Kawaguchi , Yasumitsu Nozawa
发明人： Masami Masuda , Takayuki Kawaguchi , Yasumitsu Nozawa
IPC分类号： H01L21/8249 , H01L21/8222 , H01L21/8248 , H01L27/06 , H03K17/56 , H03K19/08 , H03K19/0944 , H03K19/096 , H03K19/01 , H03K19/003 , H03K19/082 , H03K19/094
CPC分类号： H03K19/09448 , H03K19/0963
摘要： This invention is a BiMOS logical circuit that provides a suitable output level with a limited number of components. The intermediate node of a PMOS transistor and an NMOS transistor is connected to the base of a bipolar transistor to control output voltage. The NMOS transistor is connected between the output terminal and the power source, and an output voltage approximately equal to the power supply voltage is obtained at the output terminal.
摘要翻译：本发明是一种BiMOS逻辑电路，其提供具有有限数量的组件的合适的输出电平。 PMOS晶体管的中间节点和NMOS晶体管连接到双极晶体管的基极以控制输出电压。 NMOS晶体管连接在输出端子与电源之间，在输出端子处获得大致等于电源电压的输出电压。

35. 发明授权

US4769561A Bipolar transistor-field effect transistor composite circuit 失效
标题翻译：双极晶体管场效应晶体管复合电路
公开(公告)号：US4769561A
公开(公告)日：1988-09-06
申请号：US680495
申请日：1984-12-11
申请人： Masahiro Iwamura , Ikuro Masuda
发明人： Masahiro Iwamura , Ikuro Masuda
IPC分类号： H03K19/01 , H03K17/567 , H03K17/687 , H03K19/08 , H03K19/0944
CPC分类号： H03K19/09448
摘要： A bipolar transistor-complementary field effect transistor composite circuit is provided which includes a pair of first and second bipolar transistors each having a collector of a first conductivity type, a base of a second conductivity type and an emitter of a first conductivity type. Collector-emitter current paths of the bipolar transistors are connected in series to each other between first and second potentials, with a connection node providing an output of the composite circuit. Field effect transistors are respectively coupled between the bases and collectors of the bipolar transistors for controlling the on-off states of the bipolar transistors in opposite relationship to one another in response to an input signal provided to the composite circuit. Also, discharge arrangements are provided for the bases of the first and second bipolar transistors to discharge parasitic capacitance in the bases of the first and second bipolar transistors when they are turned off.
摘要翻译：提供了双极晶体管 - 互补场效应晶体管复合电路，其包括一对第一和第二双极晶体管，每个具有第一导电类型的集电极，第二导电类型的基极和第一导电类型的发射极。双极晶体管的集电极 - 发射极电流路径在第一和第二电位之间彼此串联连接，连接节点提供复合电路的输出。场效应晶体管分别耦合在双极晶体管的基极和集电极之间，用于响应于提供给复合电路的输入信号而彼此相反地控制双极晶体管的导通截止状态。此外，为第一和第二双极晶体管的基极提供放电布置，以在第一和第二双极晶体管的基极中的寄生电容被截止时放电。

36. 发明授权

US4764693A Semiconductor sense circuit suitable for buffer circuit in semiconductor memory chip 失效
标题翻译：半导体感应电路适用于半导体存储芯片中的缓冲电路
公开(公告)号：US4764693A
公开(公告)日：1988-08-16
申请号：US48813
申请日：1987-05-12
申请人： Yoshihisa Iwata
发明人： Yoshihisa Iwata
IPC分类号： G11C11/413 , G11C7/06 , G11C7/10 , G11C8/06 , G11C11/408 , H03K17/04 , H03K3/356 , H03K17/687 , H03K19/01
CPC分类号： G11C7/1057 , G11C7/065 , G11C7/1051 , G11C8/06
摘要： A sense circuit for use in a semiconductor memory senses an input signal by comparing the input signal with a reference voltage. The sense circuit comprises a sense amplifier having first and second nodes, and first and second transfer gates. The first transfer gate couples the input signal to the first node of the sense amplifier. The second transfer gate couples the reference voltage to the second node of the sense amplifier. A level-shift circuit is provided between the second node of the sense amplifier and the second transfer gate. In response to the voltage level of the input signal latched in the first node, the level-shift circuit shifts the level of the reference voltage latched in the second node of the sense amplifier to a lower level when the input signal is high in voltage level, and shifts it to a higher level when the input signal is low in voltage level.
摘要翻译：用于半导体存储器的感测电路通过将输入信号与参考电压进行比较而感测输入信号。感测电路包括具有第一和第二节点的读出放大器以及第一和第二传输门。第一传输门将输入信号耦合到读出放大器的第一节点。第二传输门将参考电压耦合到读出放大器的第二个节点。在读出放大器的第二节点和第二传输门之间提供电平移位电路。响应于在第一节点中锁存的输入信号的电压电平，当输入信号的电压电平高时，电平移位电路将读出放大器的第二节点中锁存的参考电压的电平移位到较低电平，并且当输入信号的电压电平低时，将其移动到更高的电平。

37. 发明授权

US4740718A Bi-CMOS logic circuit 失效
标题翻译：双CMOS逻辑电路
公开(公告)号：US4740718A
公开(公告)日：1988-04-26
申请号：US31923
申请日：1987-03-30
申请人： Masataka Matsui
发明人： Masataka Matsui
IPC分类号： H01L21/8249 , H01L27/06 , H03K19/013 , H03K19/08 , H03K19/0944 , H03K19/01 , H03K19/003 , H03K19/082 , H03K19/094
CPC分类号： H03K19/09448 , H03K19/0136
摘要： A Bi-CMOS logic circuit having a totem pole-type output buffer, a CMOS logic circuit, and a latch circuit. The output buffer comprises a pull-up NPN bipolar transistor and a pull-down NPN bipolar transistor. The CMOS logic circuit controls the base current of the pull-up NPN bipolar transistor. The latch circuit controls the base current of the pull-down NPN bipolar transistor. The latch circuit includes at least two N-type MOSFETs. The first MOSFET has a gate coupled to the input terminal of the CMOS logic circuit, a drain connected to the node of the first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor. The second MOSFET has a drain coupled to the input terminal of the CMOS logic circuit, a gate connected to the node of the first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor.
摘要翻译：具有图腾柱型输出缓冲器，CMOS逻辑电路和锁存电路的Bi-CMOS逻辑电路。输出缓冲器包括上拉NPN双极晶体管和下拉NPN双极晶体管。 CMOS逻辑电路控制上拉NPN双极晶体管的基极电流。锁存电路控制下拉NPN双极晶体管的基极电流。锁存电路包括至少两个N型MOSFET。第一MOSFET具有耦合到CMOS逻辑电路的输入端的栅极，连接到第一和第二NPN双极晶体管的节点的漏极和耦合到所述第二NPN双极晶体管的基极的源极。第二MOSFET具有耦合到CMOS逻辑电路的输入端的漏极，连接到第一和第二NPN双极晶体管的节点的栅极以及耦合到所述第二NPN双极晶体管的基极的源极。

38. 发明授权

US4644186A Fast switching circuit for lateral PNP transistors 失效
标题翻译：用于横向PNP晶体管的快速开关电路
公开(公告)号：US4644186A
公开(公告)日：1987-02-17
申请号：US642615
申请日：1984-08-20
申请人： Sivakumar Sivasothy , Ramanatha V. Balakrishnan
发明人： Sivakumar Sivasothy , Ramanatha V. Balakrishnan
IPC分类号： H03K17/0412 , H03K19/092 , H03K19/01
CPC分类号： H03K17/04126
摘要： A circuit (100) is shown which provides a large turn-on current drive to the base of a lateral PNP transistor (218) by forcing a large voltage drop across the base-emitter junction of the lateral PNP transistor in order to quickly turn on the PNP transistor. A current sensing circuit (203, 166) determines when the collector current in the PNP transistor is sufficient for proper operation of the rest of the circuitry dependent upon this PNP transistor. The current sensing circuitry then limits the base drive applied to the PNP transistor to the current level necessary to maintain the required quiescent collector current in the PNP transistor. In addition, means (190, 200) are provided to quickly clamp the base of the PNP transistor to the emitter of the PNP transistor thereby quickly turning off the PNP transistor.
摘要翻译：示出了通过在横向PNP晶体管的基极 - 发射极结两端施加大的电压降以便快速导通的电路（100），其向横向PNP晶体管（218）的基极提供大的导通电流驱动 PNP晶体管。电流感测电路（203,166）确定PNP晶体管中的集电极电流何时足以依赖于该PNP晶体管的其余电路的正确操作。电流检测电路然后将施加到PNP晶体管的基极驱动限制到维持PNP晶体管中所需的静态集电极电流所需的电流水平。此外，提供装置（190,200）以将PNP晶体管的基极快速钳位到PNP晶体管的发射极，从而快速关断PNP晶体管。

39. 发明授权

US4605864A AFL (advanced fast logic) line driver circuit 失效
标题翻译： AFL（高级快速逻辑）线路驱动电路
公开(公告)号：US4605864A
公开(公告)日：1986-08-12
申请号：US688719
申请日：1985-01-04
申请人： Hemmige D. Varadarajan , Nader Vasseghi
发明人： Hemmige D. Varadarajan , Nader Vasseghi
IPC分类号： H03K5/02 , H03K19/018 , H03K19/092 , H03K17/04 , H03K17/60 , H03K19/01
CPC分类号： H03K19/01831 , H03K5/02
摘要： A line driver circuit is formed of a driver circuit section and a receiver circuit section. The driver circuit section provide a low impedance drive for charging and discharging quickly a capacitive load. A receiver circuit section includes an output level-shifting transistor which is adapted for translating a voltage at an output node of the driver circuit section to a compatible higher level.
摘要翻译：线驱动电路由驱动电路部和接收电路部构成。驱动器电路部分提供低阻抗驱动器，以快速地对容性负载进行充电和放电。接收器电路部分包括输出电平移位晶体管，其适于将驱动器电路部分的输出节点处的电压转换为兼容的较高电平。

40. 发明授权

US4590392A Current feedback Schottky logic 失效
标题翻译：电流反馈肖特基逻辑
公开(公告)号：US4590392A
公开(公告)日：1986-05-20
申请号：US533715
申请日：1983-09-19
申请人： Tho T. Vu
发明人： Tho T. Vu
IPC分类号： H03K3/288 , H03K19/084 , H03K3/286 , H03K19/01 , H03K19/12
CPC分类号： H03K19/084 , H03K3/288
摘要： A bipolar OR logic circuit includes input diodes directly connected to a switching transistor. A first current source is coupled to the transistor's emitter and a load is directly connected to and between the collector and a voltage reference point. A second current source, connected to the transistor's base, sets the switching point of the transistor. The output is taken at the collector. A second bipolar transistor can be cross coupled to the first transistor to provide a voltage reference for the base of the first transistor and/or shift the logic level by taking the output at the emitter of the second transistor.
摘要翻译：双极OR逻辑电路包括直接连接到开关晶体管的输入二极管。第一电流源耦合到晶体管的发射极，负载直接连接到集电极和电压参考点之间。连接到晶体管的基极的第二个电流源设置晶体管的开关点。输出采集在收集器。第二双极晶体管可以交叉耦合到第一晶体管，以提供用于第一晶体管的基极的电压基准和/或通过取第二晶体管的发射极处的输出来移位逻辑电平。

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