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31. 发明授权

US06515912B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06515912B1
公开(公告)日：2003-02-04
申请号：US10018156
申请日：2001-12-10
申请人： Guoqiao Tao , Johannes Dijkstra , Robertus Dominicus Joseph Verhaar , Thomas James Davies
发明人： Guoqiao Tao , Johannes Dijkstra , Robertus Dominicus Joseph Verhaar , Thomas James Davies
IPC分类号： G11C1600
CPC分类号： G11C16/0441
摘要： A semiconductor device comprising a memory cell, which memory cell comprises: a write transistor (TWR) a read transistor (TRE), a sense transistor (TSE) provided with a sense transistor gate, a first sense transistor electrode (7) and a second sense transistor electrode (3), the first sense transistor electrode (7) being connected to a read transistor electrode (9), the sense transistor gate being arranged as a floating gate (FG), said floating gate being separated from the second sense electrode (3) by a sense transistor oxide layer (THINOX) and from a write transistor electrode (1) by a tunnel oxide layer (TUNOX); a voltage source arrangement (5, Vsi_p, Vsi_e) to provide the second sense transistor electrode (3) with a predetermined voltage during programming and erasing, such that no stress induced leakage current occurs in the sense transistor oxide layer (THINOX).
摘要翻译：一种包括存储单元的半导体器件，该存储单元包括：写晶体管（TWR），读晶体管（TRE），具有感测晶体管栅极的检测晶体管（TSE），第一检测晶体管电极（7）感测晶体管电极（3），所述第一感测晶体管电极（7）连接到读取晶体管电极（9），所述感测晶体管栅极被布置为浮置栅极（FG），所述浮置栅极与所述第二感测电极（3）通过感测晶体管氧化物层（THINOX）和由晶体管电极（1）通过隧道氧化物层（TUNOX）;电压源装置（5，Vsi_p，Vsi_e），以提供第二感测晶体管电极）在编程和擦除期间具有预定电压，使得在感测晶体管氧化物层（THINOX）中不产生应力感应泄漏电流。

32. 发明授权

US06496410B1 Concurrent program reconnaissance with piggyback pulses for multi-level cell flash memory designs 有权
标题翻译：并发程序侦察与搭载脉冲的多级单元闪存设计
公开(公告)号：US06496410B1
公开(公告)日：2002-12-17
申请号：US09779764
申请日：2001-02-08
申请人： Allan Parker
发明人： Allan Parker
IPC分类号： G11C1600
CPC分类号： G11C11/5628 , G11C16/12
摘要： A method of programming a memory cell that has 2N voltage levels where N>1 and represents the number of bits stored within the memory cell. The method includes setting a target number T of piggyback programming pulses for programming each of 2N−1 vt levels of the memory cell, applying T piggyback programming pulses to the memory cell and determining when the highest one of the 2N−1 vt levels is programmed. If it is determined that the highest one of the 2N−1 vt levels is programmed by a number M of piggyback programming pulses that is less than the target number T, then compensating the programming speed of those ones of said T number of piggyback programming pulses subsequent to the Mth piggyback programming pulse.
摘要翻译：一种编程具有2N电压电平的存储单元的方法，其中N≥1并且表示存储在存储单元中的位数。该方法包括设置搭载编程脉冲的目标数量T，以对存储器单元的2N-1V级别的每一个进行编程，将T个搭载编程脉冲施加到存储器单元，并确定2N-1Vt级中最高的一个是否被编程。如果确定2N-1Vt电平中最高的一个是通过小于目标数目T的数量M的搭载编程脉冲编程的，则补偿所述T个载波编程脉冲中的那些的编程速度在第M个背负编程脉冲之后。

33. 发明授权

US06483746B2 Electronic apparatus 有权
标题翻译：电子仪器
公开(公告)号：US06483746B2
公开(公告)日：2002-11-19
申请号：US09860456
申请日：2001-05-21
申请人： Masahiko Haraguchi , Hiromi Katagawa
发明人： Masahiko Haraguchi , Hiromi Katagawa
IPC分类号： G11C1600
CPC分类号： G11C16/105 , G11C16/102
摘要： There is provided an electronic apparatus that can recover easily even when failing to update version up of a program and can be started without resort to special operation even when the program changes to change the storage format of setting information. The apparatus has a central processing unit for controlling the whole of the apparatus, a writable and nonvolatile memory for storing programs and setting information and a random access memory uses as a work area. The nonvolatile memory has at least three program areas.
摘要翻译：提供一种电子装置，即使在不能更新程序的版本时也能够容易地恢复，并且即使在程序改变以改变设置信息的存储格式时也可以启动而不需要特别的操作。该装置具有用于控制整个装置的中央处理单元，用于存储程序和设置信息的可写入和非易失性存储器，随机存取存储器用作工作区域。非易失性存储器具有至少三个程序区域。

34. 发明授权

US06307784B1 Negative gate erase 有权
标题翻译：负栅极擦除
公开(公告)号：US06307784B1
公开(公告)日：2001-10-23
申请号：US09795856
申请日：2001-02-28
申请人： Darlene G. Hamilton , Narbeh Derhacobian , Kulachet Tanpairoj , Ravi Sunkavalli
发明人： Darlene G. Hamilton , Narbeh Derhacobian , Kulachet Tanpairoj , Ravi Sunkavalli
IPC分类号： G11C1600
CPC分类号： G11C16/3409 , G11C11/5671 , G11C16/0475 , G11C16/3404 , G11C16/344 , G11C16/3445 , H01L27/115
摘要： A method and system for performing verify erasure comprises applying an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. This operation is important for single power supply devices since the beginning of erase band to band currents for the entire array are larger than can be supplied by drain pumps. After the first erase pulse, the erase verify routine can be performed on all the IO's together. In one particular example, a Vdrain voltage is selected to be at a substantially high positive voltage and the value of Vgate voltage is at a substantially high negative voltage where the voltage potential between Vdrain and Vgate is also a substantially high voltage.
摘要翻译：用于执行验证擦除的方法和系统包括对一个扇区中的每个I / O提供实质上高的电场的擦除脉冲。该操作对于单个电源设备是重要的，因为整个阵列的擦除频带到带电流的开始大于由排水泵提供的带电流。在第一个擦除脉冲之后，可以在所有IO上一起执行擦除验证程序。在一个特定示例中，选择Vdrain电压处于基本上高的正电压，并且Vgate电压的值处于基本上高的负电压，其中Vdrain和Vgate之间的电压电位也是基本上高的电压。

35. 发明授权

US06240015B1 Method for reading 2-bit ETOX cells using gate induced drain leakage current 有权
标题翻译：使用栅极感应漏极漏电流读取2位ETOX单元的方法
公开(公告)号：US06240015B1
公开(公告)日：2001-05-29
申请号：US09545038
申请日：2000-04-07
申请人： Min-hwa Chi , Dahcheng Lin
发明人： Min-hwa Chi , Dahcheng Lin
IPC分类号： G11C1600
CPC分类号： G11C16/26 , G11C11/5635 , G11C11/5642 , G11C11/5671 , G11C2211/565
摘要： A method of reading a 2-bit memory cell having a drain, a source, a control gate, and a floating gate is disclosed. First, a voltage is applied to the source and drain to generate a gate induced drain leakage (GIDL) current. Next, a measurement is taken of a drain GIDL current at said drain and a source GIDL current at said source to determine the data stored in said memory cell.
摘要翻译：公开了一种读取具有漏极，源极，控制栅极和浮置栅极的2位存储单元的方法。首先，向源极和漏极施加电压以产生栅极感应漏极泄漏（GIDL）电流。接下来，测量所述漏极处的漏极GIDL电流和在所述源极处的源极GIDL电流，以确定存储在所述存储器单元中的数据。

36. 发明授权

US06822906B2 Sense amplifier structure for multilevel non-volatile memory devices and corresponding reading method 有权
标题翻译：用于多电平非易失性存储器件的感应放大器结构及相应的读取方法
公开(公告)号：US06822906B2
公开(公告)日：2004-11-23
申请号：US10331158
申请日：2002-12-26
申请人： Emanuele Confalonieri
发明人： Emanuele Confalonieri
IPC分类号： G11C1600
CPC分类号： G11C11/5621 , G11C7/06 , G11C7/062 , G11C11/56 , G11C11/5642 , G11C2207/063
摘要： A sense amplifier structure for multi-level non-volatile memories reads the contents of the memory cells. In particular, a current drawn by a memory cell to be read is compared to a current drawn by a reference cell through a sense amplifier that has one input terminal connected to a circuit node to which said currents are led. Advantageously, the currents are compared at both inputs of the sense amplifier by connecting a second input of said amplifier to a circuit node to which said currents are led, with opposite signs. The method enhances the read precision of the sense amplifier for a given data acquisition time by doubling the differential input voltage.
摘要翻译：用于多级非易失性存储器的读出放大器结构读取存储器单元的内容。特别地，将要读取的存储单元所绘制的电流与通过读出放大器所绘制的电流进行比较，所述读出放大器的一个输入端连接到所述电流被引导到的电路节点。有利地，通过将所述放大器的第二输入连接到所述电流被引导到的电路节点，以相反的符号比较在读出放大器的两个输入处的电流。该方法通过将差分输入电压加倍来提高读出放大器对给定数据采集时间的读取精度。

37. 发明授权

US06822900B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06822900B2
公开(公告)日：2004-11-23
申请号：US10115956
申请日：2002-04-05
申请人： Teruhiko Kamei
发明人： Teruhiko Kamei
IPC分类号： G11C1600
CPC分类号： G11C16/3427 , G11C7/18 , G11C16/0475 , G11C16/0491
摘要： A non-volatile semiconductor memory device has a memory cell array region in which a plurality of memory cells are disposed in both column and row directions, each of the memory cells having first and second MONOS memory cells controlled by a word gate and first and second control gates. The memory cell array region is divided in the row direction into a plurality of sector regions extending longitudinally in the column direction. Each of the sector regions is divided into a plurality of large blocks, such as eight large blocks. There are eight control gate drivers for each sector region. Each of these eight control gate drivers sets potentials for first and second control gates of all the memory cells disposed within the corresponding one block of the eight large blocks.
摘要翻译：非易失性半导体存储器件具有存储单元阵列区域，其中在列和行方向上布置多个存储单元，每个存储单元具有由字门控制的第一和第二MONOS存储单元，第一和第二控制门存储单元阵列区域在行方向上被划分为在列方向上纵向延伸的多个扇区区域。每个扇区被划分成多个大块，例如八个大块。每个扇区都有八个控制栅极驱动器。这八个控制栅极驱动器中的每一个设置了设置在八个大块的相应一个块内的所有存储单元的第一和第二控制栅极的电位。

38. 发明授权

US06799256B2 System and method for multi-bit flash reads using dual dynamic references 有权
标题翻译：使用双动态引用的多位闪存读取的系统和方法
公开(公告)号：US06799256B2
公开(公告)日：2004-09-28
申请号：US10136173
申请日：2002-05-01
申请人： Michael A. Van Buskirk , Darlene G. Hamilton , Pua-Ling Chen , Kazuhiro Kuribara
发明人： Michael A. Van Buskirk , Darlene G. Hamilton , Pua-Ling Chen , Kazuhiro Kuribara
IPC分类号： G11C1600
CPC分类号： G11C16/28 , G11C7/14 , G11C11/5642 , G11C11/5671 , G11C16/0475 , G11C2211/5634
摘要： A system and methodology is provided for proper reading of multi-bit memory cells in a memory device. A first reference cell and a second reference cell is employed to determine an average dynamic reference value. The average dynamic reference value is determined by reading a programmed bit of the first reference cell and reading an unprogrammed or erased bit of a second reference cell to determine an average dynamic reference value. The average dynamic reference value can be utilized to determine whether data cells are in a programmed state or in an unprogrammed state.
摘要翻译：提供了用于正确读取存储器件中的多位存储器单元的系统和方法。使用第一参考单元和第二参考单元来确定平均动态参考值。通过读取第一参考单元的编程位并读取第二参考单元的未编程或擦除位来确定平均动态参考值来确定平均动态参考值。平均动态参考值可用于确定数据单元是处于编程状态还是处于未编程状态。

39. 发明授权

US06788582B2 Non-volatile memory device with erase address register 失效
标题翻译：具有擦除地址寄存器的非易失性存储器件
公开(公告)号：US06788582B2
公开(公告)日：2004-09-07
申请号：US10672652
申请日：2003-09-26
申请人： Frankie F. Roohparvar
发明人： Frankie F. Roohparvar
IPC分类号： G11C1600
CPC分类号： G11C16/16 , G11C8/12 , G11C16/344
摘要： A non-volatile memory device includes an array of non-volatile memory cells. The memory has control circuitry to erase the non-volatile memory cells and perform erase verification operations. The memory can be arranged in numerous erasable blocks and/or sub-blocks. An erase register stores data indicating an erase state of corresponding memory sub-blocks. During erase verification, the memory programs the erase register when a non-erased memory cell is located in a corresponding sub-block. Additional erase pulses can be selectively applied to sub-blocks based upon the erase register data. Likewise, erase verification operations can be selectively performed on sub-blocks based upon the erase register data. An address register is provided to store an address of a non-erased memory cell identified during verification. The address from the register is used as a start address for subsequent verification operations on the same array location.
摘要翻译：非易失性存储器件包括非易失性存储器单元阵列。存储器具有用于擦除非易失性存储器单元并执行擦除验证操作的控制电路。存储器可以被布置在多个可擦除块和/或子块中。擦除寄存器存储指示相应存储器子块的擦除状态的数据。在擦除验证期间，当未擦除的存储单元位于相应的子块中时，存储器对擦除寄存器进行编程。可以基于擦除寄存器数据将附加擦除脉冲选择性地施加到子块。类似地，可以基于擦除寄存器数据在子块上选择性地执行擦除验证操作。提供地址寄存器以存储在验证期间识别的未擦除的存储器单元的地址。寄存器中的地址用作同一阵列位置后续验证操作的起始地址。

40. 发明授权

US06785161B2 High voltage regulator for low voltage integrated circuit processes 有权
标题翻译：用于低压集成电路工艺的高压调节器
公开(公告)号：US06785161B2
公开(公告)日：2004-08-31
申请号：US10184756
申请日：2002-06-28
申请人： Theodore T. Pekny
发明人： Theodore T. Pekny
IPC分类号： G11C1600
CPC分类号： G11C5/146
摘要： An improved voltage reduction circuit and method is described that incorporates an independently controllable back bias voltage for increased gate/bulk fields in isolation well voltage reduction transistors that couple to and reduce external voltages that are too high for the integrated circuit process technology limits. The improved voltage reduction circuit and method allows for a higher overall available voltage and current flow for regulation by the circuit. Additionally, the improved voltage reduction circuit and method reduces voltage reduction circuit size by allowing for efficient implementation in a single isolation well. Furthermore, the improved voltage reduction circuit and method includes a back bias voltage control circuit that turns on and regulates the back bias voltage and avoids the problem of reverse bias conditions.
摘要翻译：描述了一种改进的电压降低电路和方法，其包括独立可控的反向偏置电压，用于隔离阱电压降低晶体管中的增加的栅极/体区，其耦合到和降低对于集成电路工艺技术限制而言太高的外部电压。改进的电压降低电路和方法允许更高的总体可用电压和电流流动以供电路调节。此外，改进的电压降低电路和方法通过允许在单个隔离阱中的有效实现来降低电压降低电路尺寸。此外，改进的电压降低电路和方法包括反向偏置电压控制电路，其接通和调节背偏置电压并避免反向偏置条件的问题。

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